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2022-03-23Merge tag 'asm-generic-5.18' of ↵Linus Torvalds3-276/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic updates from Arnd Bergmann: "There are three sets of updates for 5.18 in the asm-generic tree: - The set_fs()/get_fs() infrastructure gets removed for good. This was already gone from all major architectures, but now we can finally remove it everywhere, which loses some particularly tricky and error-prone code. There is a small merge conflict against a parisc cleanup, the solution is to use their new version. - The nds32 architecture ends its tenure in the Linux kernel. The hardware is still used and the code is in reasonable shape, but the mainline port is not actively maintained any more, as all remaining users are thought to run vendor kernels that would never be updated to a future release. - A series from Masahiro Yamada cleans up some of the uapi header files to pass the compile-time checks" * tag 'asm-generic-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (27 commits) nds32: Remove the architecture uaccess: remove CONFIG_SET_FS ia64: remove CONFIG_SET_FS support sh: remove CONFIG_SET_FS support sparc64: remove CONFIG_SET_FS support lib/test_lockup: fix kernel pointer check for separate address spaces uaccess: generalize access_ok() uaccess: fix type mismatch warnings from access_ok() arm64: simplify access_ok() m68k: fix access_ok for coldfire MIPS: use simpler access_ok() MIPS: Handle address errors for accesses above CPU max virtual user address uaccess: add generic __{get,put}_kernel_nofault nios2: drop access_ok() check from __put_user() x86: use more conventional access_ok() definition x86: remove __range_not_ok() sparc64: add __{get,put}_kernel_nofault() nds32: fix access_ok() checks in get/put_user uaccess: fix nios2 and microblaze get_user_8() sparc64: fix building assembly files ...
2022-03-21Merge tag 'acpi-5.18-rc1' of ↵Linus Torvalds1-2/+4
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI updates from Rafael Wysocki: "From the new functionality perspective, the most significant items here are the new driver for the 'ARM Generic Diagnostic Dump and Reset' device, the extension of fine grain fan control in the ACPI fan driver, and the change making it possible to use CPPC information to obtain CPU capacity. There are also a few new quirks, a bunch of fixes, including the platform-level _OSC handling change to make it actually take the platform firmware response into account, some code and documentation cleanups, and a notable update of the ACPI device enumeration documentation. Specifics: - Use uintptr_t and offsetof() in the ACPICA code to avoid compiler warnings regarding NULL pointer arithmetic (Rafael Wysocki). - Fix possible NULL pointer dereference in acpi_ns_walk_namespace() when passed "acpi=off" in the command line (Rafael Wysocki). - Fix and clean up acpi_os_read/write_port() (Rafael Wysocki). - Introduce acpi_bus_for_each_dev() and use it for walking all ACPI device objects in the Type C code (Rafael Wysocki). - Fix the _OSC platform capabilities negotioation and prevent CPPC from being used if the platform firmware indicates that it not supported via _OSC (Rafael Wysocki). - Use ida_alloc() instead of ida_simple_get() for ACPI enumeration of devices (Rafael Wysocki). - Add AGDI and CEDT to the list of known ACPI table signatures (Ilkka Koskinen, Robert Kiraly). - Add power management debug messages related to suspend-to-idle in two places (Rafael Wysocki). - Fix __acpi_node_get_property_reference() return value and clean up that function (Andy Shevchenko, Sakari Ailus). - Fix return value of the __setup handler in the ACPI PM timer clock source driver (Randy Dunlap). - Clean up double words in two comments (Tom Rix). - Add "skip i2c clients" quirks for Lenovo Yoga Tablet 1050F/L and Nextbook Ares 8 (Hans de Goede). - Clean up frequency invariance handling on x86 in the ACPI CPPC library (Huang Rui). - Work around broken XSDT on the Advantech DAC-BJ01 board (Mark Cilissen). - Make wakeup events checks in the ACPI EC driver more straightforward and clean up acpi_ec_submit_event() (Rafael Wysocki). - Make it possible to obtain the CPU capacity with the help of CPPC information (Ionela Voinescu). - Improve fine grained fan control in the ACPI fan driver and document it (Srinivas Pandruvada). - Add device HID and quirk for Microsoft Surface Go 3 to the ACPI battery driver (Maximilian Luz). - Make the ACPI driver for Intel SoCs (LPSS) let the SPI driver know the exact type of the controller (Andy Shevchenko). - Force native backlight mode on Clevo NL5xRU and NL5xNU (Werner Sembach). - Fix return value of __setup handlers in the APEI code (Randy Dunlap). - Add Arm Generic Diagnostic Dump and Reset device driver (Ilkka Koskinen). - Limit printable size of BERT table data (Darren Hart). - Fix up HEST and GHES initialization (Shuai Xue). - Update the ACPI device enumeration documentation and unify the ASL style in GPIO-related examples (Andy Shevchenko)" * tag 'acpi-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (52 commits) clocksource: acpi_pm: fix return value of __setup handler ACPI: bus: Avoid using CPPC if not supported by firmware Revert "ACPI: Pass the same capabilities to the _OSC regardless of the query flag" ACPI: video: Force backlight native for Clevo NL5xRU and NL5xNU arm64, topology: enable use of init_cpu_capacity_cppc() arch_topology: obtain cpu capacity using information from CPPC x86, ACPI: rename init_freq_invariance_cppc() to arch_init_invariance_cppc() ACPI: AGDI: Add driver for Arm Generic Diagnostic Dump and Reset device ACPI: tables: Add AGDI to the list of known table signatures ACPI/APEI: Limit printable size of BERT table data ACPI: docs: gpio-properties: Unify ASL style for GPIO examples ACPI / x86: Work around broken XSDT on Advantech DAC-BJ01 board ACPI: APEI: fix return value of __setup handlers x86/ACPI: CPPC: Move init_freq_invariance_cppc() into x86 CPPC x86: Expose init_freq_invariance() to topology header x86/ACPI: CPPC: Move AMD maximum frequency ratio setting function into x86 CPPC x86/ACPI: CPPC: Rename cppc_msr.c to cppc.c ACPI / x86: Add skip i2c clients quirk for Lenovo Yoga Tablet 1050F/L ACPI / x86: Add skip i2c clients quirk for Nextbook Ares 8 ACPICA: Avoid walking the ACPI Namespace if it is not there ...
2022-03-21Merge tag 'timers-core-2022-03-21' of ↵Linus Torvalds8-39/+48
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer and timekeeping updates from Thomas Gleixner: "Core code: - Make the NOHZ handling of the timekeeping/tick core more robust to prevent a rare jiffies update stall. - Handle softirqs in the NOHZ/idle case correctly Drivers: - Add support for event stream scaling of the 1GHz counter on ARM(64) - Correct an error code check in the timer-of layer - The usual cleanups and improvements all over the place" * tag 'timers-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) lib/irq_poll: Declare IRQ_POLL softirq vector as ksoftirqd-parking safe tick/rcu: Stop allowing RCU_SOFTIRQ in idle tick/rcu: Remove obsolete rcu_needs_cpu() parameters tick: Detect and fix jiffies update stall clocksource/drivers/timer-of: Check return value of of_iomap in timer_of_base_init() clocksource/drivers/timer-microchip-pit64b: Use 5MHz for clockevent clocksource/drivers/timer-microchip-pit64b: Use notrace clocksource/drivers/timer-microchip-pit64b: Remove mmio selection dt-bindings: timer: Tegra: Convert text bindings to yaml clocksource/drivers/imx-tpm: Move tpm_read_sched_clock() under CONFIG_ARM clocksource/drivers/arm_arch_timer: Use event stream scaling when available clocksource/drivers/exynos_mct: Increase the size of name array clocksource/drivers/exynos_mct: Bump up mct max irq number clocksource/drivers/exynos_mct: Remove mct interrupt index enum clocksource/drivers/exynos_mct: Handle DTS with higher number of interrupts clocksource/drivers/timer-ti-dm: Fix regression from errata i940 fix clocksource/drivers/imx-tpm: Exclude sched clock for ARM64 clocksource: Add a Kconfig option for WATCHDOG_MAX_SKEW clocksource/drivers/imx-tpm: Update name of clkevt clocksource/drivers/imx-tpm: Add CLOCK_EVT_FEAT_DYNIRQ ...
2022-03-18Merge branches 'acpi-pm', 'acpi-properties', 'acpi-misc' and 'acpi-x86'Rafael J. Wysocki1-2/+4
Merge ACPI power management changes, ACPI device properties handling changes, x86-specific ACPI changes and miscellaneous ACPI changes for 5.18-rc1: - Add power management debug messages related to suspend-to-idle in two places (Rafael Wysocki). - Fix __acpi_node_get_property_reference() return value and clean up that function (Andy Shevchenko, Sakari Ailus). - Fix return value of the __setup handler in the ACPI PM timer clock source driver (Randy Dunlap). - Clean up double words in two comments (Tom Rix). - Add "skip i2c clients" quirks for Lenovo Yoga Tablet 1050F/L and Nextbook Ares 8 (Hans de Goede). - Clean up frequency invariance handling on x86 in the ACPI CPPC library (Huang Rui). - Work around broken XSDT on the Advantech DAC-BJ01 board (Mark Cilissen). * acpi-pm: ACPI: EC / PM: Print additional debug message in acpi_ec_dispatch_gpe() ACPI: PM: Print additional debug message in acpi_s2idle_wake() * acpi-properties: ACPI: property: Get rid of redundant 'else' ACPI: properties: Consistently return -ENOENT if there are no more references * acpi-misc: clocksource: acpi_pm: fix return value of __setup handler ACPI: clean up double words in two comments * acpi-x86: ACPI / x86: Work around broken XSDT on Advantech DAC-BJ01 board x86/ACPI: CPPC: Move init_freq_invariance_cppc() into x86 CPPC x86: Expose init_freq_invariance() to topology header x86/ACPI: CPPC: Move AMD maximum frequency ratio setting function into x86 CPPC x86/ACPI: CPPC: Rename cppc_msr.c to cppc.c ACPI / x86: Add skip i2c clients quirk for Lenovo Yoga Tablet 1050F/L ACPI / x86: Add skip i2c clients quirk for Nextbook Ares 8
2022-03-18clocksource: acpi_pm: fix return value of __setup handlerRandy Dunlap1-2/+4
__setup() handlers should return 1 to obsolete_checksetup() in init/main.c to indicate that the boot option has been handled. A return of 0 causes the boot option/value to be listed as an Unknown kernel parameter and added to init's (limited) environment strings. The __setup() handler interface isn't meant to handle negative return values -- they are non-zero, so they mean "handled" (like a return value of 1 does), but that's just a quirk. So return 1 from parse_pmtmr(). Also print a warning message if kstrtouint() returns an error. Fixes: 6b148507d3d0 ("pmtmr: allow command line override of ioport") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: Igor Zhbanov <i.zhbanov@omprussia.ru> Link: lore.kernel.org/r/64644a2f-4a20-bab3-1e15-3b2cdd0defe3@omprussia.ru Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-03-14Merge tag 'timers-v5.18-rc1' of ↵Thomas Gleixner8-39/+48
https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clocksource/events updates from Daniel Lezcano: - Fix return error code check for the timer-of layer when getting the base address (Guillaume Ranquet) - Remove MMIO dependency, add notrace annotation for sched_clock and increase the timer resolution for the Microchip PIT64b (Claudiu Beznea) - Convert DT bindings to yaml for the Tegra timer (David Heidelberg) - Fix compilation error on architecture other than ARM for the i.MX TPM (Nathan Chancellor) - Add support for the event stream scaling for 1GHz counter on the arch ARM timer (Marc Zyngier) - Support a higher number of interrupts by the Exynos MCT timer driver (Alim Akhtar) - Detect and prevent memory corruption when the specified number of interrupts in the DTS is greater than the array size in the code for the Exynos MCT timer (Krzysztof Kozlowski) - Fix regression from a previous errata fix on the TI DM timer (Drew Fustini) - Several fixes and code improvements for the i.MX TPM driver (Peng Fan) Link: https://lore.kernel.org/all/a8cd9be9-7d70-80df-2b74-1a8226a215e1@linaro.org
2022-03-07clocksource/drivers/timer-of: Check return value of of_iomap in ↵Guillaume Ranquet1-3/+3
timer_of_base_init() of_base->base can either be iomapped using of_io_request_and_map() or of_iomap() depending whether or not an of_base->name has been set. Thus check of_base->base against NULL as of_iomap() does not return a PTR_ERR() in case of error. Fixes: 9aea417afa6b ("clocksource/drivers/timer-of: Don't request the resource by name") Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Link: https://lore.kernel.org/r/20220307172656.4836-1-granquet@baylibre.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-microchip-pit64b: Use 5MHz for clockeventClaudiu Beznea1-4/+2
Use 5MHz clock for clockevent timers. This increases timer's resolution. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220304133601.2404086-4-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-microchip-pit64b: Use notraceClaudiu Beznea1-1/+1
Use notrace for mchp_pit64b_sched_read_clk() to avoid recursive call of prepare_ftrace_return() when issuing: echo function_graph > /sys/kernel/debug/tracing/current_tracer Fixes: 625022a5f160 ("clocksource/drivers/timer-microchip-pit64b: Add Microchip PIT64B support") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220304133601.2404086-3-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-microchip-pit64b: Remove mmio selectionClaudiu Beznea1-1/+0
PIT64B timer driver doesn't depend on CLKSRC_MMIO since commit e85c1d21b16b ("clocksource/drivers/timer-microchip-pit64b: Add clocksource suspend/resume"). Remove the selection. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220304133601.2404086-2-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/imx-tpm: Move tpm_read_sched_clock() under CONFIG_ARMNathan Chancellor1-1/+1
When building this driver for an architecture other than ARCH=arm: drivers/clocksource/timer-imx-tpm.c:78:20: error: unused function 'tpm_read_sched_clock' [-Werror,-Wunused-function] static u64 notrace tpm_read_sched_clock(void) ^ 1 error generated. Move the function definition under the existing CONFIG_ARM section so there is no more warning. Fixes: 10720e120e2b ("clocksource/drivers/imx-tpm: Exclude sched clock for ARM64") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220303184212.2356245-1-nathan@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/arm_arch_timer: Use event stream scaling when availableMarc Zyngier1-2/+11
With FEAT_ECV and the 1GHz counter, it is pretty likely that the event stream divider doesn't fit in the field that holds the divider value (we only have 4 bits to describe counter bits [15:0] Thankfully, FEAT_ECV also provides a scaling mechanism to switch the field to cover counter bits [23:8] instead. Enable this on arm64 when ECV is available (32bit doesn't have any detection infrastructure and is unlikely to be run on an ARMv8.6 system anyway). Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220203170502.2694422-1-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Increase the size of name arrayAlim Akhtar1-1/+5
Variable _name_ hold mct_tick number per cpu and it is currently limited to 10. Which restrict the scalability of the MCT driver for the SoC which has more local timers interrupts (>= 12). Increase the length of it to make mct_tick printed correctly for each local timer interrupts per CPU. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220221174547.26176-3-alim.akhtar@samsung.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Bump up mct max irq numberAlim Akhtar1-1/+2
Bump-up maximum number of MCT IRQ to match the binding documentation. This make driver scalable for SoC which has more than 12 timer irqs, like recently added FSD SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220221174547.26176-2-alim.akhtar@samsung.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Remove mct interrupt index enumAlim Akhtar1-16/+6
MCT driver define an enum which list global and local timer's irq index. Most of them are not used but MCT_G0_IRQ and MCT_L0_IRQ and these two are at a fixed offset/index. Get rid of this enum and use a #define for the used irq index. No functional changes expected. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220221174547.26176-1-alim.akhtar@samsung.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Handle DTS with higher number of interruptsKrzysztof Kozlowski1-1/+9
The driver statically defines maximum number of interrupts it can handle, however it does not respect that limit when configuring them. When provided with a DTS with more interrupts than assumed, the driver will overwrite static array mct_irqs leading to silent memory corruption. Validate the interrupts coming from DTS to avoid this. This does not change the fact that such DTS might not boot at all, because it is simply incompatible, however at least some warning will be printed. Fixes: 36ba5d527e95 ("ARM: EXYNOS: add device tree support for MCT controller driver") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220220103815.135380-1-krzysztof.kozlowski@canonical.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-ti-dm: Fix regression from errata i940 fixDrew Fustini1-2/+2
The existing fix for errata i940 causes a conflict for IPU2 which is using timer 3 and 4. From arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi: &ipu2 { mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; ti,timers = <&timer3>; ti,watchdog-timers = <&timer4>, <&timer9>; }; The conflict was noticed when booting mainline on the BeagleBoard X15 which has a TI AM5728 SoC: remoteproc remoteproc1: 55020000.ipu is available remoteproc remoteproc1: powering up 55020000.ipu remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4 omap-rproc 55020000.ipu: could not get timer platform device omap-rproc 55020000.ipu: omap_rproc_enable_timers failed: -19 remoteproc remoteproc1: can't start rproc 55020000.ipu: -19 This change modifies the errata fix to instead use timer 15 and 16 which resolves the timer conflict. It does not appear to introduce any latency regression. Results from cyclictest with original errata fix using dmtimer 3 and 4: # cyclictest --mlockall --smp --priority=80 --interval=200 --distance=0 policy: fifo: loadavg: 0.02 0.03 0.05 T: 0 ( 1449) P:80 I:200 C: 800368 Min: 0 Act: 32 Avg: 22 Max: 128 T: 1 ( 1450) P:80 I:200 C: 800301 Min: 0 Act: 12 Avg: 23 Max: 70 The results after the change to dmtimer 15 and 16: # cyclictest --mlockall --smp --priority=80 --interval=200 --distance=0 policy: fifo: loadavg: 0.36 0.19 0.07 T: 0 ( 1711) P:80 I:200 C: 759599 Min: 0 Act: 6 Avg: 22 Max: 108 T: 1 ( 1712) P:80 I:200 C: 759539 Min: 0 Act: 19 Avg: 23 Max: 79 Fixes: 25de4ce5ed02 ("clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940") Link: https://lore.kernel.org/linux-omap/YfWsG0p6to3IJuvE@x1/ Suggested-by: Suman Anna <s-anna@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Link: https://lore.kernel.org/r/20220204053503.1409162-1-dfustini@baylibre.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07nds32: Remove the architectureAlan Kao3-276/+0
The nds32 architecture, also known as AndeStar V3, is a custom 32-bit RISC target designed by Andes Technologies. Support was added to the kernel in 2016 as the replacement RISC-V based V5 processors were already announced, and maintained by (current or former) Andes employees. As explained by Alan Kao, new customers are now all using RISC-V, and all known nds32 users are already on longterm stable kernels provided by Andes, with no development work going into mainline support any more. While the port is still in a reasonably good shape, it only gets worse over time without active maintainers, so it seems best to remove it before it becomes unusable. As always, if it turns out that there are mainline users after all, and they volunteer to maintain the port in the future, the removal can be reverted. Link: https://lore.kernel.org/linux-mm/YhdWNLUhk+x9RAzU@yamatobi.andestech.com/ Link: https://lore.kernel.org/lkml/20220302065213.82702-1-alankao@andestech.com/ Link: https://www.andestech.com/en/products-solutions/andestar-architecture/ Signed-off-by: Alan Kao <alankao@andestech.com> [arnd: rewrite changelog to provide more background] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-02-18ARM: dts: Use 32KiHz oscillator on devkit8000Anthoine Bourgeois1-2/+1
Devkit8000 board seems to always used 32k_counter as clocksource. Restore this behavior. If clocksource is back to 32k_counter, timer12 is now the clockevent source (as before) and timer2 is not longer needed here. This commit fixes the same issue observed with commit 23885389dbbb ("ARM: dts: Fix timer regression for beagleboard revision c") when sleep is blocked until hitting keys over serial console. Fixes: aba1ad05da08 ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support") Fixes: e428e250fde6 ("ARM: dts: Configure system timers for omap3") Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-02-16clocksource/drivers/imx-tpm: Exclude sched clock for ARM64Peng Fan1-1/+1
For ARM64 platform such as i.MX8ULP which has ARMv8 generic timer as sched clock, which is much faster compared with tpm sched clock. Reading the tpm count register in i.MX8ULP requires about 290ns, this is slow and introduce scheduler latency. So exclude tpm sched clock for ARM64 platform. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220105124304.3567629-1-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-02-07Merge tag 'omap-for-v5.17/fixes-for-merge-window-signed' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes Fixes for omaps A series of fixes for omap variants for minor issues, and a fix for a timer regression for some omap3 beagleboard versions. The timer fix needs to patch both the dts and the timer code because otherwise the timer quirk handling for old dtbs will prevent the dts fix from working. The other changes are for issues found by automated analysis, a macasp typo fix, and two cosmetic fixes for clocks. * tag 'omap-for-v5.17/fixes-for-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: Don't use legacy clock defines for dra7 clkctrl clk: ti: Move dra7 clock devices out of the legacy section ARM: dts: Fix timer regression for beagleboard revision c ARM: dts: am335x-wega: Fix typo in mcasp property rx-num-evt ARM: OMAP2+: adjust the location of put_device() call in omapdss_init_of ARM: OMAP2+: hwmod: Add of_node_put() before break Link: https://lore.kernel.org/r/pull-1641801310-149268@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-01-26clocksource/drivers/imx-tpm: Update name of clkevtPeng Fan1-1/+1
The tpm driver is not only for i.MX7ULP now, i.MX8ULP also use it. It maybe also used by other i.MX variants, so update name to reflect it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20211214120737.1611955-6-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-01-26clocksource/drivers/imx-tpm: Add CLOCK_EVT_FEAT_DYNIRQPeng Fan1-1/+1
Add CLOCK_EVT_FEAT_DYNIRQ to allow the IRQ could be runtime set affinity to the cores that needs wake up, otherwise saying core0 has to send IPI to wakeup core1. With CLOCK_EVT_FEAT_DYNIRQ set, when broadcast timer could wake up the cores, IPI is not needed. Acked-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20211214120737.1611955-5-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-01-26clocksource/drivers/imx-tpm: Mark two variable with __ro_after_initPeng Fan1-2/+2
counter_width and timer_base will not be updated after init, so mark as __ro_after_init. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20211214120737.1611955-4-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-01-26clocksource/drivers/imx-tpm: Drop IRQF_IRQPOLLPeng Fan1-1/+1
Per the Documentation, IRQF_IRQPOLL is used for polling (only the interrupt that is registered first in a shared interrupt is considered for performance reasons) The TPM timer is not sharing interrupt with others, and pass irqpoll not make sense for i.MX platform. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20211214120737.1611955-3-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-01-26clocksource/drivers/imx-sysctr: Drop IRQF_IRQPOLLPeng Fan1-1/+1
Per the Documentation, IRQF_IRQPOLL is used for polling (only the interrupt that is registered first in a shared interrupt is considered for performance reasons) But this timer is not sharing interrupt line with others, and actually irqpoll not work with this timer with IRQF_IRQPOLL set, so drop the flag. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20211214120737.1611955-2-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-01-10Merge tag 'timers-v5.17-rc1' of ↵Thomas Gleixner7-27/+339
https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clocksource/events updates from Daniel Lezcano: - Refactor resource allocation on the Exynos_mct driver without functional changes (Marek Szyprowski) - Add imx8ulp compatible string for NPX TPM driver (Jacky Bai) - Fix comma introduced by error by replacing it by the initial semicolon on the Exynos_mct (Will Deacon) - Add OSTM driver support on Renesas. The reset line must be deasserted before accessing the registers. This change depends on an external change resulting in a shared immutable branch 'reset/of-get-optional-exclusive' from git://git.pengutronix.de/pza/linux (Biju Das) - Make the OSTM Kconfig option visible to user in order to let him disable it when ARM architected timers is enabled (Biju Das) - Tag two variables on iMX sysctr _ro_afterinit (Peng Fan) - Set the cpumask to cpu_possible_mask in order to have full benefit of the DYNIRQ flag on iMX sysctr (Peng Fan) - Tag __maybe_unused a variable in the Pistachio timer driver in order to fix a warning reported by the kernel test robot (Drew Fustini) - Add MStar MSC313e timer support and the ssd20xd-based variant, as well as the DT bindings (Romain Perier) - Remove the incompatible compatible string for the rk3066 (Johan Jonker) - Fix dts_check warnings on the cadence ttc driver by adding the power domain bindings (Michal Simek) Link: https://lore.kernel.org/lkml/e093c706-c98d-29ee-0102-78b6d41c6164@linaro.org
2021-12-20clocksource/drivers/msc313e: Add support for ssd20xd-based platformsRomain Perier1-0/+9
On SSD20X family SoCs the timers are connected to a 432MHz clock instead of 12MHz that all the previous chips used. There is no way to reduce or divide these clocks in the clktree yet as we do not know exactly where the 432MHz clock comes from but it is enabled at boot. The SSD20X timers have an input clock divider within the timer itself to configure the frequency. timer0 is preconfigured at power up to run at 12MHz so it is backwards compatible and doesn't need special handling right now. timer1 and timer2 run at 432Mhz at power up so are not backward compatible. This commit adds support for the input clock divider register and sets timer1 and timer2 to run at 48Mhz for clockevents. Signed-off-by: Romain Perier <romain.perier@gmail.com> Link: https://lore.kernel.org/r/20211217195727.8955-3-romain.perier@gmail.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-20clocksource/drivers: Add MStar MSC313e timer supportRomain Perier3-0/+254
The MSC313e-compatible SoCs have 3 timer hardware blocks. All of these are free running 32-bit increasing counters and can generate interrupts. Based onto a maximum value register, each timer can either count from 0 to max, one time then stop (which generates interrupts) or can count from 0 to max and then roll. This commit adds basic support for these timers, the first timer block being used as clocksource/sched_clock and delay, while the others will be used as clockevents. Signed-off-by: Romain Perier <romain.perier@gmail.com> Co-developed-by: Daniel Palmer <daniel@0x0f.com> Signed-off-by: Daniel Palmer <daniel@0x0f.com> Link: https://lore.kernel.org/r/20211217195727.8955-2-romain.perier@gmail.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-17ARM: dts: Fix timer regression for beagleboard revision cTony Lindgren1-1/+1
Commit e428e250fde6 ("ARM: dts: Configure system timers for omap3") caused a timer regression for beagleboard revision c where the system clockevent stops working if omap3isp module is unloaded. Turns out we still have beagleboard revisions a-b4 capacitor c70 quirks applied that limit the usable timers for no good reason. This also affects the power management as we use the system clock instead of the 32k clock source. Let's fix the issue by adding a new omap3-beagle-ab4.dts for the old timer quirks. This allows us to remove the timer quirks for later beagleboard revisions. We also need to update the related timer quirk check for the correct compatible property. Fixes: e428e250fde6 ("ARM: dts: Configure system timers for omap3") Cc: linux-kernel@vger.kernel.org Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <robh+dt@kernel.org> Reported-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Tested-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-12-14clocksource/drivers/pistachio: Fix -Wunused-but-set-variable warningDrew Fustini1-1/+2
Variable 'overflow' set but not used, but this is the intended behavior. The hardware only updates the counter register after the overflow register read. However, the value of overflow is not actually needed. Link: https://lore.kernel.org/lkml/202111200402.afQsussU-lkp@intel.com/ Reported-by: kernel test robot <lkp@intel.com> Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Link: https://lore.kernel.org/r/20211123192524.1038304-1-dfustini@baylibre.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-14clocksource/drivers/timer-imx-sysctr: Set cpumask to cpu_possible_maskPeng Fan1-1/+1
The syctr interrupt could set the affinity to any cores in the SoC. However, the default affinity is set to cpu 0. This timer will be used as broadcast timer on all the i.MX SoCs. Because DYNIRQ flag is set, the core time framework will runtime set the interrupt affinity to the cores that needs to wake up and the cpumask will runtime set to the core that will be wake up. So even the sysctr initialization use cpumask 0, there is no issue, the current patch is just use cpu_possible_mask to show the fact that the timer supports routed to all the cpu cores and nothing else. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20211201125030.2307746-2-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-10clocksource/drivers/arm_arch_timer: Force inlining of ↵Marc Zyngier1-2/+7
erratum_set_next_event_generic() With some specific kernel configuration and Clang, the kernel fails to like with something like: ld.lld: error: undefined symbol: __compiletime_assert_200 >>> referenced by arch_timer.h:156 (./arch/arm64/include/asm/arch_timer.h:156) >>> clocksource/arm_arch_timer.o:(erratum_set_next_event_generic) in archive drivers/built-in.a ld.lld: error: undefined symbol: __compiletime_assert_197 >>> referenced by arch_timer.h:133 (./arch/arm64/include/asm/arch_timer.h:133) >>> clocksource/arm_arch_timer.o:(erratum_set_next_event_generic) in archive drivers/built-in.a make: *** [Makefile:1161: vmlinux] Error 1 These are due to the BUILD_BUG() macros contained in the low-level accessors (arch_timer_reg_{write,read}_cp15) being emitted, as the access type wasn't known at compile time. Fix this by making erratum_set_next_event_generic() __force_inline, resulting in the 'access' parameter to be resolved at compile time, similarly to what is already done for set_next_event(). Fixes: 4775bc63f880 ("Add build-time guards for unhandled register accesses") Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Sami Tolvanen <samitolvanen@google.com> Cc: Nick Desaulniers <ndesaulniers@google.com> Tested-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20211117113532.3895208-1-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-10clocksource/drivers/dw_apb_timer_of: Fix probe failureAlexey Sheplyakov1-1/+1
The driver refuses to probe with -EINVAL since the commit 5d9814df0aec ("clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available"). Before the driver used to probe successfully if either "clock-freq" or "clock-frequency" properties has been specified in the device tree. That commit changed if (A && B) panic("No clock nor clock-frequency property"); into if (!A && !B) return 0; That's a bug: the reverse of `A && B` is '!A || !B', not '!A && !B' Signed-off-by: Vadim V. Vlasov <vadim.vlasov@elpitech.ru> Signed-off-by: Alexey Sheplyakov <asheplyakov@basealt.ru> Fixes: 5d9814df0aec56a6 ("clocksource/drivers/dw_apb_timer_of: Add error handling if no clock available"). Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vadim V. Vlasov <vadim.vlasov@elpitech.ru> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20211109153401.157491-1-asheplyakov@basealt.ru Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-09clocksource/drivers/imx-sysctr: Mark two variable with __ro_after_initPeng Fan1-2/+2
The variables 'sys_ctr_base' and 'cmpcr' are not be updated after init, so mark them as __ro_after_init. Cc: Kees Cook <keescook@chromium.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Kees Cook <keescook@chromium.org> Link: https://lore.kernel.org/r/20211201125030.2307746-1-peng.fan@oss.nxp.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-09clocksource/drivers/renesas,ostm: Make RENESAS_OSTM symbol visibleBiju Das1-1/+2
As RZ/G2L uses the ARM Architected Timer as system timer, enabling the OSTM is not mandatory. Make RENESAS_OSTM symbol visible, so that user can enable it when needed. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20211112184413.4391-5-biju.das.jz@bp.renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-09clocksource/drivers/renesas-ostm: Add RZ/G2L OSTM supportBiju Das1-1/+38
RZ/G2L SoC has Generic Timer Module(a.k.a OSTM) which needs to deassert the reset line before accessing any registers. This patch adds an entry point for RZ/G2L so that we can deassert the reset line in probe callback. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20211112184413.4391-4-biju.das.jz@bp.renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-09Merge branch 'reset/of-get-optional-exclusive' of ↵Daniel Lezcano4-16/+47
git://git.pengutronix.de/pza/linux into timers/drivers/next "Add optional variant of of_reset_control_get_exclusive(). If the requested reset is not specified in the device tree, this function returns NULL instead of an error." This dependency is needed for the Generic Timer Module (a.k.a OSTM) support for RZ/G2L. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-12-09clocksource/drivers/exynos_mct: Fix silly typo resulting in checkpatch warningWill Deacon1-1/+1
Commit ae460fd9164b ("clocksource/drivers/exynos_mct: Prioritise Arm arch timer on arm64") changed the rating of the MCT clockevents device to be lower than the Arm architected timer and, in the process, replaced a semicolon with a comma thanks to a silly copy-paste error. Put the semicolon back so that the code looks more idiomatic and resolve the SUSPECT_COMMA_SEMICOLON warning from checkpatch at the same time. Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Will Deacon <will@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211103164804.30182-1-will@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-11-16clocksource/drivers/exynos_mct: Refactor resources allocationMarek Szyprowski1-20/+30
Move interrupts allocation from exynos4_timer_resources() into separate function together with the interrupt number parsing code from mct_init_dt(), so the code for managing interrupts is kept together. While touching exynos4_timer_resources() function, move of_iomap() to it. No functional changes. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211101193531.15078-2-semen.protsenko@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-11-02Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+9
Pull KVM updates from Paolo Bonzini: "ARM: - More progress on the protected VM front, now with the full fixed feature set as well as the limitation of some hypercalls after initialisation. - Cleanup of the RAZ/WI sysreg handling, which was pointlessly complicated - Fixes for the vgic placement in the IPA space, together with a bunch of selftests - More memcg accounting of the memory allocated on behalf of a guest - Timer and vgic selftests - Workarounds for the Apple M1 broken vgic implementation - KConfig cleanups - New kvmarm.mode=none option, for those who really dislike us RISC-V: - New KVM port. x86: - New API to control TSC offset from userspace - TSC scaling for nested hypervisors on SVM - Switch masterclock protection from raw_spin_lock to seqcount - Clean up function prototypes in the page fault code and avoid repeated memslot lookups - Convey the exit reason to userspace on emulation failure - Configure time between NX page recovery iterations - Expose Predictive Store Forwarding Disable CPUID leaf - Allocate page tracking data structures lazily (if the i915 KVM-GT functionality is not compiled in) - Cleanups, fixes and optimizations for the shadow MMU code s390: - SIGP Fixes - initial preparations for lazy destroy of secure VMs - storage key improvements/fixes - Log the guest CPNC Starting from this release, KVM-PPC patches will come from Michael Ellerman's PPC tree" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (227 commits) RISC-V: KVM: fix boolreturn.cocci warnings RISC-V: KVM: remove unneeded semicolon RISC-V: KVM: Fix GPA passed to __kvm_riscv_hfence_gvma_xyz() functions RISC-V: KVM: Factor-out FP virtualization into separate sources KVM: s390: add debug statement for diag 318 CPNC data KVM: s390: pv: properly handle page flags for protected guests KVM: s390: Fix handle_sske page fault handling KVM: x86: SGX must obey the KVM_INTERNAL_ERROR_EMULATION protocol KVM: x86: On emulation failure, convey the exit reason, etc. to userspace KVM: x86: Get exit_reason as part of kvm_x86_ops.get_exit_info KVM: x86: Clarify the kvm_run.emulation_failure structure layout KVM: s390: Add a routine for setting userspace CPU state KVM: s390: Simplify SIGP Set Arch handling KVM: s390: pv: avoid stalls when making pages secure KVM: s390: pv: avoid stalls for kvm_s390_pv_init_vm KVM: s390: pv: avoid double free of sida page KVM: s390: pv: add macros for UVC CC values s390/mm: optimize reset_guest_reference_bit() s390/mm: optimize set_guest_storage_key() s390/mm: no need for pte_alloc_map_lock() if we know the pmd is present ...
2021-11-01Merge tag 'timers-core-2021-10-31' of ↵Linus Torvalds3-99/+153
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer updates from Thomas Gleixner: "Time, timers and timekeeping updates: - No core updates - No new clocksource/event driver - A large rework of the ARM architected timer driver to prepare for the support of the upcoming ARMv8.6 support - Fix Kconfig options for Exynos MCT, Samsung PWM and TI DM timers - Address a namespace collison in the ARC sp804 timer driver" * tag 'timers-core-2021-10-31' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource/drivers/timer-ti-dm: Select TIMER_OF clocksource/drivers/exynosy: Depend on sub-architecture for Exynos MCT and Samsung PWM clocksource/drivers/arch_arm_timer: Move workaround synchronisation around clocksource/drivers/arm_arch_timer: Fix masking for high freq counters clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming clocksource/drivers/arm_arch_timer: Remove any trace of the TVAL programming interface clocksource/drivers/arm_arch_timer: Work around broken CVAL implementations clocksource/drivers/arm_arch_timer: Advertise 56bit timer to the core code clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL clocksource/drivers/arm_arch_timer: Fix MMIO base address vs callback ordering issue clocksource/drivers/arm_arch_timer: Move drop _tval from erratum function names clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL clocksource/drivers/arm_arch_timer: Extend write side of timer register accessors to u64 clocksource/drivers/arm_arch_timer: Drop CNT*_TVAL read accessors clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses clocksource/drivers/arc_timer: Eliminate redefined macro error
2021-10-21clocksource/drivers/timer-ti-dm: Select TIMER_OFKees Cook1-0/+1
When building OMAP_DM_TIMER without TIMER_OF, there are orphan sections due to the use of TIMER_OF_DELCARE() without CONFIG_TIMER_OF. Select CONFIG_TIMER_OF when enaling OMAP_DM_TIMER: arm-linux-gnueabi-ld: warning: orphan section `__timer_of_table' from `drivers/clocksource/timer-ti-dm-systimer.o' being placed in section `__timer_of_table' Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/lkml/202108282255.tkdt4ani-lkp@intel.com/ Cc: Tony Lindgren <tony@atomide.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Keerthy <j-keerthy@ti.com> Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Cc: linux-omap@vger.kernel.org Fixes: 52762fbd1c47 ("clocksource/drivers/timer-ti-dm: Add clockevent and clocksource support") Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210828175747.3777891-1-keescook@chromium.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-10-21clocksource/drivers/exynosy: Depend on sub-architecture for Exynos MCT and ↵Krzysztof Kozlowski1-0/+2
Samsung PWM The Exynos MCT and Samsung PWM Timer clocksource drivers are not usable on anything else than Samsung Exynos, S3C or S5P SoC platforms. These are integral parts of a SoC. Even though the drivers are not user selectable, still document the hardware architecture explicitly with depends on ARCH_EXYNOS and others. This also serves a purpose of documenting use-case, if someone ever wonders whether to select the driver for his platform. No functional change, because drivers are already selected by the platform described in depends. We follow similar approach also for other SoC-specific drivers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211021063500.39314-1-krzysztof.kozlowski@canonical.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-10-19Merge branch 'timers/drivers/armv8.6_arch_timer' into timers/drivers/nextDaniel Lezcano1-96/+147
The branch is a stable branch shared with ARM maintainers for the first 13th patches of the series: It is based on v5.14-rc3. As stated by the changelog: " [... ] enabling ARMv8.6 support for timer subsystem, and was prompted by a discussion with Oliver around the fact that an ARMv8.6 implementation must have a 1GHz counter, which leads to a number of things to break in the timer code: - the counter rollover can come pretty quickly as we only advertise a 56bit counter, - the maximum timer delta can be remarkably small, as we use the countdown interface which is limited to 32bit... Thankfully, there is a way out: we can compute the minimal width of the counter based on the guarantees that the architecture gives us, and we can use the 64bit comparator interface instead of the countdown to program the timer. Finally, we start making use of the ARMv8.6 ECV features by switching accesses to the counters to a self-synchronising register, removing the need for an ISB. Hopefully, implementations will *not* just stick an invisible ISB there... A side effect of the switch to CVAL is that XGene-1 breaks. I have added a workaround to keep it alive. I have added Oliver's original patch[0] to the series and tweaked a couple of things. Blame me if I broke anything. The whole things has been tested on Juno (sysreg + MMIO timers), XGene-1 (broken sysreg timers), FVP (FEAT_ECV, CNT*CTSS_EL0). " Link: https://lore.kernel.org/r/20211017124225.3018098-1-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-10-18clocksource/drivers/arm_arch_timer: Fix masking for high freq countersOliver Upton1-5/+29
Unfortunately, the architecture provides no means to determine the bit width of the system counter. However, we do know the following from the specification: - the system counter is at least 56 bits wide - Roll-over time of not less than 40 years To date, the arch timer driver has depended on the first property, assuming any system counter to be 56 bits wide and masking off the rest. However, combining a narrow clocksource mask with a high frequency counter could result in prematurely wrapping the system counter by a significant margin. For example, a 56 bit wide, 1GHz system counter would wrap in a mere 2.28 years! This is a problem for two reasons: v8.6+ implementations are required to provide a 64 bit, 1GHz system counter. Furthermore, before v8.6, implementers may select a counter frequency of their choosing. Fix the issue by deriving a valid clock mask based on the second property from above. Set the floor at 56 bits, since we know no system counter is narrower than that. [maz: fixed width computation not to lose the last bit, added max delta generation for the timer] Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Oliver Upton <oupton@google.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210807191428.3488948-1-oupton@google.com Link: https://lore.kernel.org/r/20211017124225.3018098-13-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-10-17clocksource/drivers/arm_arch_timer: Remove any trace of the TVAL programming ↵Marc Zyngier1-8/+0
interface TVAL usage is now long gone, get rid of the leftovers. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211017124225.3018098-11-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-10-17clocksource/drivers/arm_arch_timer: Work around broken CVAL implementationsMarc Zyngier1-1/+27
The Applied Micro XGene-1 SoC has a busted implementation of the CVAL register: it looks like it is based on TVAL instead of the other way around. The net effect of this implementation blunder is that the maximum deadline you can program in the timer is 32bit wide. Use a MIDR check to notice the broken CPU, and reduce the width of the timer to 32bit. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211017124225.3018098-10-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-10-17clocksource/drivers/arm_arch_timer: Advertise 56bit timer to the core codeMarc Zyngier1-1/+1
Proudly tell the code code that we have a timer able to handle 56 bits deltas. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211017124225.3018098-9-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2021-10-17clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVALMarc Zyngier1-12/+38
Similarily to the sysreg-based timer, move the MMIO over to using the CVAL registers instead of TVAL. Note that there is no warranty that the 64bit MMIO access will be atomic, but the timer is always disabled at the point where we program CVAL. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211017124225.3018098-8-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>