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2022-07-19riscv: cpu: Add 64bit hartid support on RV64Sunil V L1-7/+8
The hartid can be a 64bit value on RV64 platforms. Add support for 64bit hartid in riscv_of_processor_hartid() and update its callers. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20220527051743.2829940-5-sunilvl@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-07-18clocksource/drivers/sh_cmt: Add R-Car Gen4 supportWolfram Sang1-0/+8
Add support for the R-Car Gen4 CMT types 0/1 which are the same as in the previous two generations. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220713100603.3391-4-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-07-16clocksource/drivers/timer-microchip-pit64b: Fix compilation warningsClaudiu Beznea1-4/+6
Fix the following compilation warnings: timer-microchip-pit64b.c:68: warning: cannot understand function prototype: 'struct mchp_pit64b_clkevt ' timer-microchip-pit64b.c:82: warning: cannot understand function prototype: 'struct mchp_pit64b_clksrc ' timer-microchip-pit64b.c:283: warning: Function parameter or member 'timer' not described in 'mchp_pit64b_init_mode' timer-microchip-pit64b.c:283: warning: Function parameter or member 'max_rate' not described in 'mchp_pit64b_init_mode' Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609094041.1796372-4-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-07-16clocksource/drivers/timer-microchip-pit64b: Use mchp_pit64b_{suspend, resume}Claudiu Beznea1-19/+5
Use mchp_pit64b_suspend() and mchp_pit64b_resume() to disable or enable timers clocks on init and remove specific clk_prepare_{disable, enable} calls. This is ok also for clockevent timer as proper clock enable, disable is done on .set_state_oneshot, .set_state_periodic, .set_state_shutdown calls. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609094041.1796372-3-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-07-16clocksource/drivers/timer-microchip-pit64b: Remove suspend/resume ops for ceClaudiu Beznea1-14/+16
Remove suspend and resume ops for clockevent and add set_state_oneshot() instead. Along with this mchp_pit64b_{suspend, resume}() were called on proper function to disable/enable clocks. This will allow disabling clocks for clockevent in case it is not selected as active clockevent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609094041.1796372-2-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-07-16clocksource/drivers/timer-mediatek: Implement CPUXGPT timersAngeloGioacchino Del Regno1-0/+114
Some MediaTek platforms with a buggy TrustZone ATF firmware will not initialize the AArch64 System Timer correctly: in these cases, the System Timer address is correctly programmed, as well as the CNTFRQ_EL0 register (reading 13MHz, as it should be), but the assigned hardware timers are never started before (or after) booting Linux. In this condition, any call to function get_cycles() will be returning zero, as CNTVCT_EL0 will always read zero. One common critical symptom of that is trying to use the udelay() function (calling __delay()), which executes the following loop: start = get_cycles(); while ((get_cycles() - start) < cycles) cpu_relax(); which, when CNTVCT_EL0 always reads zero, translates to: while((0 - 0) < 0) ==> while(0 < 0) ... generating an infinite loop, even though zero is never less than zero, but always equal to it (this has to be researched, but it's out of the scope of this commit). To fix this issue on the affected MediaTek platforms, the solution is to simply start the timers that are designed to be System Timer(s). These timers, downstream, are called "CPUXGPT" and there is one timer per CPU core; luckily, it is not necessary to set a start bit on each CPUX General Purpose Timer, but it's conveniently enough to: - Set the clock divider (input = 26MHz, divider = 2, output = 13MHz); - Set the ENABLE bit on a global register (starts all CPUX timers). The only small hurdle with this setup is that it's all done through the MCUSYS wrapper, where it is needed, for each read or write, to select a register address (by writing it to an index register) and then to perform any R/W on a "CON" register. For example, writing "0x1" to the CPUXGPT register offset 0x4: - Write 0x4 to mcusys INDEX register - Write 0x1 to mcusys CON register Reading from CPUXGPT register offset 0x4: - Write 0x4 to mcusys INDEX register - Read mcusys CON register. Finally, starting this timer makes platforms affected by this issue to work correctly. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220613133819.35318-3-angelogioacchino.delregno@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-07-16clocksource/drivers/timer-tegra186: Add support for Tegra234 SoCKartik1-0/+6
The timer IP block present on Tegra234 SoC supports watchdog timer functionality that can be used to recover from system hangs. The watchdog timer uses a timer in the background for countdown. Signed-off-by: Kartik <kkartik@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/1656922422-25823-4-git-send-email-kkartik@nvidia.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-07-16clocksource: Add Tegra186 timers supportThierry Reding3-0/+517
Currently this only supports a single watchdog, which uses a timer in the background for countdown. Eventually the timers could be used for various time-keeping tasks, but by default the architected timer will already provide that functionality. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/1656922422-25823-3-git-send-email-kkartik@nvidia.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-07-16clocksource/drivers/arm_global_timer: Fix Kconfig "its" grammarRandy Dunlap1-1/+1
Use the possessive "its" instead of the contraction "it's" where appropriate. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220715015852.12523-1-rdunlap@infradead.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-06-08clocksource: hyper-v: unexport __init-annotated hv_init_clocksource()Masahiro Yamada1-1/+0
EXPORT_SYMBOL and __init is a bad combination because the .init.text section is freed up after the initialization. Hence, modules cannot use symbols annotated __init. The access to a freed symbol may end up with kernel panic. modpost used to detect it, but it has been broken for a decade. Recently, I fixed modpost so it started to warn it again, then this showed up in linux-next builds. There are two ways to fix it: - Remove __init - Remove EXPORT_SYMBOL I chose the latter for this case because the only in-tree call-site, arch/x86/kernel/cpu/mshyperv.c is never compiled as modular. (CONFIG_HYPERVISOR_GUEST is boolean) Fixes: dd2cb348613b ("clocksource/drivers: Continue making Hyper-V clocksource ISA agnostic") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com> Link: https://lore.kernel.org/r/20220606050238.4162200-1-masahiroy@kernel.org Signed-off-by: Wei Liu <wei.liu@kernel.org>
2022-06-05Merge tag 'timers-core-2022-06-05' of ↵Linus Torvalds16-87/+21
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull clockevent/clocksource updates from Thomas Gleixner: - Device tree bindings for MT8186 - Tell the kernel that the RISC-V SBI timer stops in deeper power states - Make device tree parsing in sp804 more robust - Dead code removal and tiny fixes here and there - Add the missing SPDX identifiers * tag 'timers-core-2022-06-05' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clocksource/drivers/oxnas-rps: Fix irq_of_parse_and_map() return value clocksource/drivers/timer-ti-dm: Remove unnecessary NULL check clocksource/drivers/timer-sun5i: Convert to SPDX identifier clocksource/drivers/timer-sun4i: Convert to SPDX identifier clocksource/drivers/pistachio: Convert to SPDX identifier clocksource/drivers/orion: Convert to SPDX identifier clocksource/drivers/lpc32xx: Convert to SPDX identifier clocksource/drivers/digicolor: Convert to SPDX identifier clocksource/drivers/armada-370-xp: Convert to SPDX identifier clocksource/drivers/mips-gic-timer: Convert to SPDX identifier clocksource/drivers/jcore: Convert to SPDX identifier clocksource/drivers/bcm_kona: Convert to SPDX identifier clocksource/drivers/sp804: Avoid error on multiple instances clocksource/drivers/riscv: Events are stopped during CPU suspend clocksource/drivers/ixp4xx: Drop boardfile probe path dt-bindings: timer: Add compatible for Mediatek MT8186
2022-05-27Merge branch 'hpe/gxp-soc' into arm/lateArnd Bergmann3-0/+218
Patch series from Nick Hawkins: "The GXP is the HPE BMC SoC that is used in the majority of HPE current generation servers. Traditionally the asic will last multiple generations of server before being replaced. Info about SoC: HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC features at HPE. It supports ARMv7 architecture based on the Cortex A9 core. It is capable of using an AXI bus to which a memory controller is attached. It has multiple SPI interfaces to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple i2c engines to drive connectivity with a host infrastructure. The initial patches enable the watchdog and timer enabling the host to be able to boot." * hpe/gxp-soc: MAINTAINERS: Introduce HPE GXP Architecture ARM: dts: Introduce HPE GXP Device tree dt-bindings: arm: hpe: add GXP Support dt-bindings: timer: hpe,gxp-timer: Add HPE GXP Timer and Watchdog clocksource/drivers/timer-gxp: Add HPE GXP Timer watchdog: hpe-wdt: Introduce HPE GXP Watchdog ARM: configs: multi_v7_defconfig: Add HPE GXP ARCH ARM: hpe: Introduce the HPE GXP architecture Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-26Merge tag 'asm-generic-5.19' of ↵Linus Torvalds5-584/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic updates from Arnd Bergmann: "The asm-generic tree contains three separate changes for linux-5.19: - The h8300 architecture is retired after it has been effectively unmaintained for a number of years. This is the last architecture we supported that has no MMU implementation, but there are still a few architectures (arm, m68k, riscv, sh and xtensa) that support CPUs with and without an MMU. - A series to add a generic ticket spinlock that can be shared by most architectures with a working cmpxchg or ll/sc type atomic, including the conversion of riscv, csky and openrisc. This series is also a prerequisite for the loongarch64 architecture port that will come as a separate pull request. - A cleanup of some exported uapi header files to ensure they can be included from user space without relying on other kernel headers" * tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: h8300: remove stale bindings and symlink sparc: add asm/stat.h to UAPI compile-test coverage powerpc: add asm/stat.h to UAPI compile-test coverage mips: add asm/stat.h to UAPI compile-test coverage riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage kbuild: prevent exported headers from including <stdlib.h>, <stdbool.h> agpgart.h: do not include <stdlib.h> from exported header csky: Move to generic ticket-spinlock RISC-V: Move to queued RW locks RISC-V: Move to generic spinlocks openrisc: Move to ticket-spinlock asm-generic: qrwlock: Document the spinlock fairness requirements asm-generic: qspinlock: Indicate the use of mixed-size atomics asm-generic: ticket-lock: New generic ticket-based spinlock remove the h8300 architecture
2022-05-26Merge tag 'arm-multiplatform-5.19-1' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARMv4T/v5 multiplatform support from Arnd Bergmann: "This series has been 12 years in the making, it mostly finishes the work that was started with the founding of Linaro to clean up platform support in the kernel. The largest change here is a cleanup of the omap1 platform, which is the final ARM machine type to get converted to the common-clk subsystem. All the omap1 specific drivers are now made independent of the mach/*.h headers to allow the platform to be part of a generic ARMv4/v5 multiplatform kernel. The last bit that enables this support is still missing here while we wait for some last dependencies to make it into the mainline kernel through other subsystems. The s3c24xx, ixp4xx, iop32x, ep93xx and dove platforms were all almost at the point of allowing multiplatform kernels, this work gets completed here along with a few additional cleanup. At the same time, the s3c24xx and s3c64xx are now deprecated and expected to get removed in the future. The PXA and OMAP1 bits are in a separate branch because of dependencies. Once both branches are merged, only the three Intel StrongARM platforms (RiscPC, Footbridge/NetWinder and StrongARM1100) need separate kernels, and there are no plans to include these" * tag 'arm-multiplatform-5.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (61 commits) ARM: ixp4xx: Consolidate Kconfig fixing issue ARM: versatile: Add missing of_node_put in dcscb_init ARM: config: Refresh IXP4xx config after multiplatform ARM: omap1: add back omap_set_dma_priority() stub ARM: omap: fix missing declaration warnings ARM: omap: fix address space warnings from sparse ARM: spear: remove include/mach/ subdirectory ARM: davinci: remove include/mach/ subdirectory ARM: omap2: remove include/mach/ subdirectory integrator: remove empty ap_init_early() ARM: s3c: fix include path MAINTAINERS: omap1: Add Janusz as an additional maintainer ARM: omap1: htc_herald: fix typos in comments ARM: OMAP1: fix typos in comments ARM: OMAP1: clock: Remove noop code ARM: OMAP1: clock: Remove unused code ARM: OMAP1: clock: Fix UART rate reporting algorithm ARM: OMAP1: clock: Fix early UART rate issues ARM: OMAP1: Prepare for conversion of OMAP1 clocks to CCF ARM: omap1: fix build with no SoC selected ...
2022-05-24clocksource/drivers/oxnas-rps: Fix irq_of_parse_and_map() return valueKrzysztof Kozlowski1-1/+1
The irq_of_parse_and_map() returns 0 on failure, not a negative ERRNO. Fixes: 89355274e1f7 ("clocksource/drivers/oxnas-rps: Add Oxford Semiconductor RPS Dual Timer") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220422104101.55754-1-krzysztof.kozlowski@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-24clocksource/drivers/timer-ti-dm: Remove unnecessary NULL checkDan Carpenter1-2/+1
The "pdata" pointer cannot be NULL because it's checked at the start of the function. Delete the check. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/YoZM65RFDQAfqV6J@kili Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/timer-gxp: Add HPE GXP TimerNick Hawkins3-0/+218
Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 32 bits. The timer also creates a child watchdog device as the register region is the same. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-18clocksource/drivers/timer-sun5i: Convert to SPDX identifierThomas Gleixner1-4/+1
The license information clearly states GPL version 2 only. The extra text which excludes warranties is an excerpt of the corresponding GPLv2 clause 11. So the SPDX identifier covers it completely. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Samuel Holland <samuel@sholland.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-sunxi@lists.linux.dev Link: https://lore.kernel.org/r/20220510171254.970933294@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/timer-sun4i: Convert to SPDX identifierThomas Gleixner1-4/+1
The license information clearly states GPL version 2 only. The extra text which excludes warranties is an excerpt of the corresponding GPLv2 clause 11. So the SPDX identifier covers it completely. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Samuel Holland <samuel@sholland.org> Cc: linux-sunxi@lists.linux.dev Link: https://lore.kernel.org/r/20220510171254.908144392@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/pistachio: Convert to SPDX identifierThomas Gleixner1-4/+1
The licensing text references explicitely the COPYING file in the kernel base directory, which is clearly GPL version 2 only. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20220510171254.843410802@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/orion: Convert to SPDX identifierThomas Gleixner1-4/+1
The license information clearly states GPL version 2 only. The extra text which excludes warranties is an excerpt of the corresponding GPLv2 clause 11. So the SPDX identifier covers it completely. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20220510171254.780389240@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/lpc32xx: Convert to SPDX identifierThomas Gleixner1-5/+1
The license information clearly states GPL version 2 only. The extra text which excludes warranties is an excerpt of the corresponding GPLv2 clause 11. So the SPDX identifier covers it completely. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Joachim Eastwood <manabian@gmail.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Acked-by: Vladimir Zapolskiy <vz@mleia.com> Link: https://lore.kernel.org/r/20220510171254.717233312@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/digicolor: Convert to SPDX identifierThomas Gleixner1-4/+1
The license information clearly states GPL version 2 only. The extra text which excludes warranties is an excerpt of the corresponding GPLv2 clause 11. So the SPDX identifier covers it completely. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Baruch Siach <baruch@tkos.co.il> Cc: linux-arm-kernel@lists.infradead.org Acked-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/20220510171254.655035023@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/armada-370-xp: Convert to SPDX identifierThomas Gleixner1-4/+1
The license information clearly states GPL version 2 only. The extra text which excludes warranties is an excerpt of the corresponding GPLv2 clause 11. So the SPDX identifier covers it completely. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Gregory Clement <gregory.clement@free-electrons.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20220510171254.592781786@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/mips-gic-timer: Convert to SPDX identifierThomas Gleixner1-7/+2
The licensing text references explicitely the COPYING file in the kernel base directory, which is clearly GPL version 2 only. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Serge Semin <fancer.lancer@gmail.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-mips@vger.kernel.org Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220510171254.529249404@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/jcore: Convert to SPDX identifierThomas Gleixner1-4/+1
The licensing text references explicitely the COPYING file in the kernel base directory, which is clearly GPL version 2 only. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Rich Felker <dalias@libc.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20220510171254.467236056@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/bcm_kona: Convert to SPDX identifierThomas Gleixner1-12/+2
The license information clearly states GPL version 2 only. The extra text which excludes warranties is a transcript of the corresponding GPLv2 clause 11, which is explicitely referenced for details. So the SPDX identifier covers it completely. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Broadcom Kernel Team <bcm-kernel-feedback-list@broadcom.com> Cc: linux-spdx@vger.kernel.org Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220510171254.404209482@linutronix.de Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/sp804: Avoid error on multiple instancesAndre Przywara1-5/+5
When a machine sports more than one SP804 timer instance, we only bring up the first one, since multiple timers of the same kind are not useful to Linux. As this is intentional behaviour, we should not return an error message, as we do today: =============== [ 0.000800] Failed to initialize '/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/timer@120000': -22 =============== Replace the -EINVAL return with a debug message and return 0 instead. Also we do not reach the init function anymore if the DT node is disabled (as this is now handled by OF_DECLARE), so remove the explicit check for that case. This fixes a long standing bogus error when booting ARM's fastmodels. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20220506162522.3675399-1-andre.przywara@arm.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/riscv: Events are stopped during CPU suspendSamuel Holland1-1/+1
Some implementations of the SBI time extension depend on hart-local state (for example, CSRs) that are lost or hardware that is powered down when a CPU is suspended. To be safe, the clockevents driver cannot assume that timer IRQs will be received during CPU suspend. Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver") Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20220509012121.40031-1-samuel@sholland.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-05-18clocksource/drivers/ixp4xx: Drop boardfile probe pathLinus Walleij2-26/+1
The boardfiles for IXP4xx have been deleted. Delete all the quirks and code dealing with that boot path and rely solely on device tree boot. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220406205505.2332821-1-linus.walleij@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-04-21clocksource: ti-dmtimer: avoid using mach/hardware.hArnd Bergmann1-1/+1
As a preparation for future omap1 multiplatform support, stop using mach/hardware.h and instead include the omap1-io.h for low-level register access to MOD_CONF_CTRL_1. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-04-11clocksource/drivers: Add a goldfish-timer clocksourceLaurent Vivier3-0/+161
Add a clocksource based on the goldfish-rtc device. Move the timer register definition to <clocksource/timer-goldfish.h> This kernel implementation is based on the QEMU upstream implementation: https://git.qemu.org/?p=qemu.git;a=blob_plain;f=hw/rtc/goldfish_rtc.c goldfish-timer is a high-precision signed 64-bit nanosecond timer. It is part of the 'goldfish' virtual hardware platform used to run some emulated Android systems under QEMU. This timer only supports oneshot event. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20220406201523.243733-4-laurent@vivier.eu Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2022-04-04Merge branch 'remove-h8300' of git://git.infradead.org/users/hch/misc into ↵Arnd Bergmann5-584/+0
asm-generic * 'remove-h8300' of git://git.infradead.org/users/hch/misc: remove the h8300 architecture This is clearly the least actively maintained architecture we have at the moment, and probably the least useful. It is now the only one that does not support MMUs at all, and most of the boards only support 4MB of RAM, out of which the defconfig kernel needs more than half just for .text/.data. Guenter Roeck did the original patch to remove the architecture in 2013 after it had already been obsolete for a while, and Yoshinori Sato brought it back in a much more modern form in 2015. Looking at the git history since the reinstantiation, it's clear that almost all commits in the tree are build fixes or cross-architecture cleanups: $ git log --no-merges --format=%an v4.5.. arch/h8300/ | sort | uniq -c | sort -rn | head -n 12 25 Masahiro Yamada 18 Christoph Hellwig 14 Mike Rapoport 9 Arnd Bergmann 8 Mark Rutland 7 Peter Zijlstra 6 Kees Cook 6 Ingo Molnar 6 Al Viro 5 Randy Dunlap 4 Yury Norov Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-03-23Merge tag 'asm-generic-5.18' of ↵Linus Torvalds3-276/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic updates from Arnd Bergmann: "There are three sets of updates for 5.18 in the asm-generic tree: - The set_fs()/get_fs() infrastructure gets removed for good. This was already gone from all major architectures, but now we can finally remove it everywhere, which loses some particularly tricky and error-prone code. There is a small merge conflict against a parisc cleanup, the solution is to use their new version. - The nds32 architecture ends its tenure in the Linux kernel. The hardware is still used and the code is in reasonable shape, but the mainline port is not actively maintained any more, as all remaining users are thought to run vendor kernels that would never be updated to a future release. - A series from Masahiro Yamada cleans up some of the uapi header files to pass the compile-time checks" * tag 'asm-generic-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: (27 commits) nds32: Remove the architecture uaccess: remove CONFIG_SET_FS ia64: remove CONFIG_SET_FS support sh: remove CONFIG_SET_FS support sparc64: remove CONFIG_SET_FS support lib/test_lockup: fix kernel pointer check for separate address spaces uaccess: generalize access_ok() uaccess: fix type mismatch warnings from access_ok() arm64: simplify access_ok() m68k: fix access_ok for coldfire MIPS: use simpler access_ok() MIPS: Handle address errors for accesses above CPU max virtual user address uaccess: add generic __{get,put}_kernel_nofault nios2: drop access_ok() check from __put_user() x86: use more conventional access_ok() definition x86: remove __range_not_ok() sparc64: add __{get,put}_kernel_nofault() nds32: fix access_ok() checks in get/put_user uaccess: fix nios2 and microblaze get_user_8() sparc64: fix building assembly files ...
2022-03-21Merge tag 'acpi-5.18-rc1' of ↵Linus Torvalds1-2/+4
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI updates from Rafael Wysocki: "From the new functionality perspective, the most significant items here are the new driver for the 'ARM Generic Diagnostic Dump and Reset' device, the extension of fine grain fan control in the ACPI fan driver, and the change making it possible to use CPPC information to obtain CPU capacity. There are also a few new quirks, a bunch of fixes, including the platform-level _OSC handling change to make it actually take the platform firmware response into account, some code and documentation cleanups, and a notable update of the ACPI device enumeration documentation. Specifics: - Use uintptr_t and offsetof() in the ACPICA code to avoid compiler warnings regarding NULL pointer arithmetic (Rafael Wysocki). - Fix possible NULL pointer dereference in acpi_ns_walk_namespace() when passed "acpi=off" in the command line (Rafael Wysocki). - Fix and clean up acpi_os_read/write_port() (Rafael Wysocki). - Introduce acpi_bus_for_each_dev() and use it for walking all ACPI device objects in the Type C code (Rafael Wysocki). - Fix the _OSC platform capabilities negotioation and prevent CPPC from being used if the platform firmware indicates that it not supported via _OSC (Rafael Wysocki). - Use ida_alloc() instead of ida_simple_get() for ACPI enumeration of devices (Rafael Wysocki). - Add AGDI and CEDT to the list of known ACPI table signatures (Ilkka Koskinen, Robert Kiraly). - Add power management debug messages related to suspend-to-idle in two places (Rafael Wysocki). - Fix __acpi_node_get_property_reference() return value and clean up that function (Andy Shevchenko, Sakari Ailus). - Fix return value of the __setup handler in the ACPI PM timer clock source driver (Randy Dunlap). - Clean up double words in two comments (Tom Rix). - Add "skip i2c clients" quirks for Lenovo Yoga Tablet 1050F/L and Nextbook Ares 8 (Hans de Goede). - Clean up frequency invariance handling on x86 in the ACPI CPPC library (Huang Rui). - Work around broken XSDT on the Advantech DAC-BJ01 board (Mark Cilissen). - Make wakeup events checks in the ACPI EC driver more straightforward and clean up acpi_ec_submit_event() (Rafael Wysocki). - Make it possible to obtain the CPU capacity with the help of CPPC information (Ionela Voinescu). - Improve fine grained fan control in the ACPI fan driver and document it (Srinivas Pandruvada). - Add device HID and quirk for Microsoft Surface Go 3 to the ACPI battery driver (Maximilian Luz). - Make the ACPI driver for Intel SoCs (LPSS) let the SPI driver know the exact type of the controller (Andy Shevchenko). - Force native backlight mode on Clevo NL5xRU and NL5xNU (Werner Sembach). - Fix return value of __setup handlers in the APEI code (Randy Dunlap). - Add Arm Generic Diagnostic Dump and Reset device driver (Ilkka Koskinen). - Limit printable size of BERT table data (Darren Hart). - Fix up HEST and GHES initialization (Shuai Xue). - Update the ACPI device enumeration documentation and unify the ASL style in GPIO-related examples (Andy Shevchenko)" * tag 'acpi-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (52 commits) clocksource: acpi_pm: fix return value of __setup handler ACPI: bus: Avoid using CPPC if not supported by firmware Revert "ACPI: Pass the same capabilities to the _OSC regardless of the query flag" ACPI: video: Force backlight native for Clevo NL5xRU and NL5xNU arm64, topology: enable use of init_cpu_capacity_cppc() arch_topology: obtain cpu capacity using information from CPPC x86, ACPI: rename init_freq_invariance_cppc() to arch_init_invariance_cppc() ACPI: AGDI: Add driver for Arm Generic Diagnostic Dump and Reset device ACPI: tables: Add AGDI to the list of known table signatures ACPI/APEI: Limit printable size of BERT table data ACPI: docs: gpio-properties: Unify ASL style for GPIO examples ACPI / x86: Work around broken XSDT on Advantech DAC-BJ01 board ACPI: APEI: fix return value of __setup handlers x86/ACPI: CPPC: Move init_freq_invariance_cppc() into x86 CPPC x86: Expose init_freq_invariance() to topology header x86/ACPI: CPPC: Move AMD maximum frequency ratio setting function into x86 CPPC x86/ACPI: CPPC: Rename cppc_msr.c to cppc.c ACPI / x86: Add skip i2c clients quirk for Lenovo Yoga Tablet 1050F/L ACPI / x86: Add skip i2c clients quirk for Nextbook Ares 8 ACPICA: Avoid walking the ACPI Namespace if it is not there ...
2022-03-21Merge tag 'timers-core-2022-03-21' of ↵Linus Torvalds8-39/+48
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer and timekeeping updates from Thomas Gleixner: "Core code: - Make the NOHZ handling of the timekeeping/tick core more robust to prevent a rare jiffies update stall. - Handle softirqs in the NOHZ/idle case correctly Drivers: - Add support for event stream scaling of the 1GHz counter on ARM(64) - Correct an error code check in the timer-of layer - The usual cleanups and improvements all over the place" * tag 'timers-core-2022-03-21' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) lib/irq_poll: Declare IRQ_POLL softirq vector as ksoftirqd-parking safe tick/rcu: Stop allowing RCU_SOFTIRQ in idle tick/rcu: Remove obsolete rcu_needs_cpu() parameters tick: Detect and fix jiffies update stall clocksource/drivers/timer-of: Check return value of of_iomap in timer_of_base_init() clocksource/drivers/timer-microchip-pit64b: Use 5MHz for clockevent clocksource/drivers/timer-microchip-pit64b: Use notrace clocksource/drivers/timer-microchip-pit64b: Remove mmio selection dt-bindings: timer: Tegra: Convert text bindings to yaml clocksource/drivers/imx-tpm: Move tpm_read_sched_clock() under CONFIG_ARM clocksource/drivers/arm_arch_timer: Use event stream scaling when available clocksource/drivers/exynos_mct: Increase the size of name array clocksource/drivers/exynos_mct: Bump up mct max irq number clocksource/drivers/exynos_mct: Remove mct interrupt index enum clocksource/drivers/exynos_mct: Handle DTS with higher number of interrupts clocksource/drivers/timer-ti-dm: Fix regression from errata i940 fix clocksource/drivers/imx-tpm: Exclude sched clock for ARM64 clocksource: Add a Kconfig option for WATCHDOG_MAX_SKEW clocksource/drivers/imx-tpm: Update name of clkevt clocksource/drivers/imx-tpm: Add CLOCK_EVT_FEAT_DYNIRQ ...
2022-03-18Merge branches 'acpi-pm', 'acpi-properties', 'acpi-misc' and 'acpi-x86'Rafael J. Wysocki1-2/+4
Merge ACPI power management changes, ACPI device properties handling changes, x86-specific ACPI changes and miscellaneous ACPI changes for 5.18-rc1: - Add power management debug messages related to suspend-to-idle in two places (Rafael Wysocki). - Fix __acpi_node_get_property_reference() return value and clean up that function (Andy Shevchenko, Sakari Ailus). - Fix return value of the __setup handler in the ACPI PM timer clock source driver (Randy Dunlap). - Clean up double words in two comments (Tom Rix). - Add "skip i2c clients" quirks for Lenovo Yoga Tablet 1050F/L and Nextbook Ares 8 (Hans de Goede). - Clean up frequency invariance handling on x86 in the ACPI CPPC library (Huang Rui). - Work around broken XSDT on the Advantech DAC-BJ01 board (Mark Cilissen). * acpi-pm: ACPI: EC / PM: Print additional debug message in acpi_ec_dispatch_gpe() ACPI: PM: Print additional debug message in acpi_s2idle_wake() * acpi-properties: ACPI: property: Get rid of redundant 'else' ACPI: properties: Consistently return -ENOENT if there are no more references * acpi-misc: clocksource: acpi_pm: fix return value of __setup handler ACPI: clean up double words in two comments * acpi-x86: ACPI / x86: Work around broken XSDT on Advantech DAC-BJ01 board x86/ACPI: CPPC: Move init_freq_invariance_cppc() into x86 CPPC x86: Expose init_freq_invariance() to topology header x86/ACPI: CPPC: Move AMD maximum frequency ratio setting function into x86 CPPC x86/ACPI: CPPC: Rename cppc_msr.c to cppc.c ACPI / x86: Add skip i2c clients quirk for Lenovo Yoga Tablet 1050F/L ACPI / x86: Add skip i2c clients quirk for Nextbook Ares 8
2022-03-18clocksource: acpi_pm: fix return value of __setup handlerRandy Dunlap1-2/+4
__setup() handlers should return 1 to obsolete_checksetup() in init/main.c to indicate that the boot option has been handled. A return of 0 causes the boot option/value to be listed as an Unknown kernel parameter and added to init's (limited) environment strings. The __setup() handler interface isn't meant to handle negative return values -- they are non-zero, so they mean "handled" (like a return value of 1 does), but that's just a quirk. So return 1 from parse_pmtmr(). Also print a warning message if kstrtouint() returns an error. Fixes: 6b148507d3d0 ("pmtmr: allow command line override of ioport") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: Igor Zhbanov <i.zhbanov@omprussia.ru> Link: lore.kernel.org/r/64644a2f-4a20-bab3-1e15-3b2cdd0defe3@omprussia.ru Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-03-14Merge tag 'timers-v5.18-rc1' of ↵Thomas Gleixner8-39/+48
https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clocksource/events updates from Daniel Lezcano: - Fix return error code check for the timer-of layer when getting the base address (Guillaume Ranquet) - Remove MMIO dependency, add notrace annotation for sched_clock and increase the timer resolution for the Microchip PIT64b (Claudiu Beznea) - Convert DT bindings to yaml for the Tegra timer (David Heidelberg) - Fix compilation error on architecture other than ARM for the i.MX TPM (Nathan Chancellor) - Add support for the event stream scaling for 1GHz counter on the arch ARM timer (Marc Zyngier) - Support a higher number of interrupts by the Exynos MCT timer driver (Alim Akhtar) - Detect and prevent memory corruption when the specified number of interrupts in the DTS is greater than the array size in the code for the Exynos MCT timer (Krzysztof Kozlowski) - Fix regression from a previous errata fix on the TI DM timer (Drew Fustini) - Several fixes and code improvements for the i.MX TPM driver (Peng Fan) Link: https://lore.kernel.org/all/a8cd9be9-7d70-80df-2b74-1a8226a215e1@linaro.org
2022-03-07clocksource/drivers/timer-of: Check return value of of_iomap in ↵Guillaume Ranquet1-3/+3
timer_of_base_init() of_base->base can either be iomapped using of_io_request_and_map() or of_iomap() depending whether or not an of_base->name has been set. Thus check of_base->base against NULL as of_iomap() does not return a PTR_ERR() in case of error. Fixes: 9aea417afa6b ("clocksource/drivers/timer-of: Don't request the resource by name") Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> Link: https://lore.kernel.org/r/20220307172656.4836-1-granquet@baylibre.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-microchip-pit64b: Use 5MHz for clockeventClaudiu Beznea1-4/+2
Use 5MHz clock for clockevent timers. This increases timer's resolution. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220304133601.2404086-4-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-microchip-pit64b: Use notraceClaudiu Beznea1-1/+1
Use notrace for mchp_pit64b_sched_read_clk() to avoid recursive call of prepare_ftrace_return() when issuing: echo function_graph > /sys/kernel/debug/tracing/current_tracer Fixes: 625022a5f160 ("clocksource/drivers/timer-microchip-pit64b: Add Microchip PIT64B support") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220304133601.2404086-3-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-microchip-pit64b: Remove mmio selectionClaudiu Beznea1-1/+0
PIT64B timer driver doesn't depend on CLKSRC_MMIO since commit e85c1d21b16b ("clocksource/drivers/timer-microchip-pit64b: Add clocksource suspend/resume"). Remove the selection. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220304133601.2404086-2-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/imx-tpm: Move tpm_read_sched_clock() under CONFIG_ARMNathan Chancellor1-1/+1
When building this driver for an architecture other than ARCH=arm: drivers/clocksource/timer-imx-tpm.c:78:20: error: unused function 'tpm_read_sched_clock' [-Werror,-Wunused-function] static u64 notrace tpm_read_sched_clock(void) ^ 1 error generated. Move the function definition under the existing CONFIG_ARM section so there is no more warning. Fixes: 10720e120e2b ("clocksource/drivers/imx-tpm: Exclude sched clock for ARM64") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220303184212.2356245-1-nathan@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/arm_arch_timer: Use event stream scaling when availableMarc Zyngier1-2/+11
With FEAT_ECV and the 1GHz counter, it is pretty likely that the event stream divider doesn't fit in the field that holds the divider value (we only have 4 bits to describe counter bits [15:0] Thankfully, FEAT_ECV also provides a scaling mechanism to switch the field to cover counter bits [23:8] instead. Enable this on arm64 when ECV is available (32bit doesn't have any detection infrastructure and is unlikely to be run on an ARMv8.6 system anyway). Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20220203170502.2694422-1-maz@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Increase the size of name arrayAlim Akhtar1-1/+5
Variable _name_ hold mct_tick number per cpu and it is currently limited to 10. Which restrict the scalability of the MCT driver for the SoC which has more local timers interrupts (>= 12). Increase the length of it to make mct_tick printed correctly for each local timer interrupts per CPU. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220221174547.26176-3-alim.akhtar@samsung.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Bump up mct max irq numberAlim Akhtar1-1/+2
Bump-up maximum number of MCT IRQ to match the binding documentation. This make driver scalable for SoC which has more than 12 timer irqs, like recently added FSD SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220221174547.26176-2-alim.akhtar@samsung.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Remove mct interrupt index enumAlim Akhtar1-16/+6
MCT driver define an enum which list global and local timer's irq index. Most of them are not used but MCT_G0_IRQ and MCT_L0_IRQ and these two are at a fixed offset/index. Get rid of this enum and use a #define for the used irq index. No functional changes expected. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220221174547.26176-1-alim.akhtar@samsung.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/exynos_mct: Handle DTS with higher number of interruptsKrzysztof Kozlowski1-1/+9
The driver statically defines maximum number of interrupts it can handle, however it does not respect that limit when configuring them. When provided with a DTS with more interrupts than assumed, the driver will overwrite static array mct_irqs leading to silent memory corruption. Validate the interrupts coming from DTS to avoid this. This does not change the fact that such DTS might not boot at all, because it is simply incompatible, however at least some warning will be printed. Fixes: 36ba5d527e95 ("ARM: EXYNOS: add device tree support for MCT controller driver") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220220103815.135380-1-krzysztof.kozlowski@canonical.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2022-03-07clocksource/drivers/timer-ti-dm: Fix regression from errata i940 fixDrew Fustini1-2/+2
The existing fix for errata i940 causes a conflict for IPU2 which is using timer 3 and 4. From arch/arm/boot/dts/dra7-ipu-dsp-common.dtsi: &ipu2 { mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; ti,timers = <&timer3>; ti,watchdog-timers = <&timer4>, <&timer9>; }; The conflict was noticed when booting mainline on the BeagleBoard X15 which has a TI AM5728 SoC: remoteproc remoteproc1: 55020000.ipu is available remoteproc remoteproc1: powering up 55020000.ipu remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4 omap-rproc 55020000.ipu: could not get timer platform device omap-rproc 55020000.ipu: omap_rproc_enable_timers failed: -19 remoteproc remoteproc1: can't start rproc 55020000.ipu: -19 This change modifies the errata fix to instead use timer 15 and 16 which resolves the timer conflict. It does not appear to introduce any latency regression. Results from cyclictest with original errata fix using dmtimer 3 and 4: # cyclictest --mlockall --smp --priority=80 --interval=200 --distance=0 policy: fifo: loadavg: 0.02 0.03 0.05 T: 0 ( 1449) P:80 I:200 C: 800368 Min: 0 Act: 32 Avg: 22 Max: 128 T: 1 ( 1450) P:80 I:200 C: 800301 Min: 0 Act: 12 Avg: 23 Max: 70 The results after the change to dmtimer 15 and 16: # cyclictest --mlockall --smp --priority=80 --interval=200 --distance=0 policy: fifo: loadavg: 0.36 0.19 0.07 T: 0 ( 1711) P:80 I:200 C: 759599 Min: 0 Act: 6 Avg: 22 Max: 108 T: 1 ( 1712) P:80 I:200 C: 759539 Min: 0 Act: 19 Avg: 23 Max: 79 Fixes: 25de4ce5ed02 ("clocksource/drivers/timer-ti-dm: Handle dra7 timer wrap errata i940") Link: https://lore.kernel.org/linux-omap/YfWsG0p6to3IJuvE@x1/ Suggested-by: Suman Anna <s-anna@ti.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Link: https://lore.kernel.org/r/20220204053503.1409162-1-dfustini@baylibre.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-29 16:52:08 +0000