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2017-02-25Merge tag 'clk-for-linus' of ↵Linus Torvalds99-1376/+10103
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
2017-02-23Merge tag 'armsoc-dt' of ↵Linus Torvalds1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Arnd Bergmann: "A total of 380 patches this time, mostly adding support for more hardware in the device tree descriptions. There is not much exciting here for 4.11, but I've tried my best to condense the information from the pull requests I got into a readable summary. Noteworthy changes to existing platforms include: - The GIC memory map was a bit wrong almost everywhere and now gets fixed up - The Allwinner platforms convert to the generic pinmux properties - The Marvell EBU platforms now use the new DSA binding - Samsung Exynos4212 was unused and gets removed - The Renesas power management got improved New production machines: - Lego Mindstorms EV3: https://www.lego.com/en-us/mindstorms/about-ev3 - Beelink X2 Android media box: http://linux-sunxi.org/Beelink_X2 - "Romulus" baseboard management controller for OpenPower - Axentia TSE-850 Data Radio Channel (DARC) encoder: http://www.axentia.se/db/equipment.html - Luxul XAP-1410 and XWR-1200 wireless access points: https://luxul.com/xap-1410 New SoCs: - Allwinner H2+ and V3s, both minor variations of already supported chips: http://www.allwinnertech.com/index.php?c=product&a=index&id=38 - Marvell Prestera DX packet processors based on Armada XP architecture: http://www.marvell.com/switching/prestera-dx/ - Samsung Exynos4412 Prime gets added, a minor variation of Exynos4412 New developer and reference boards: - Lichee Pi One, Lichee Pi Zero and Orange Pi Zero, all based on Allwinner SoCs: http://linux-sunxi.org/LicheePi_One http://www.orangepi.org/orangepizero/ - SAMA5d36ek Reference platform: http://www.atmel.com/tools/sama5d36-ek.aspx - Beaglebone Green Wireless and Black Wireless: https://beagleboard.org/black-wireless https://beagleboard.org/green-wireless - phyCORE-AM335x System on Module: http://phytec.com/products/system-on-modules/phycore/am335x/ - New revision of "vf610-zii" Zodiac Inflight Innovations board - Various i.MX System-on-Module: Is.IoT MX6UL, SavageBoard, Engicam i.Core: http://www.opossom.com/english/index.html http://www.savageboard.org/ http://www.engicam.com/en/products/embedded/som/sodimm/is-iot-mx6ul http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q - Liebherr (LWN) monitor 6 based on i.MX6 Quad, no idea what this is - Cleanups and bugfixes on at91, bcm53xx, i.MX, mvebu, omap, oxnas, qcom, rockchip, sti, stm32 and tegra New device supports added to some boards and SoCs, briefly by platform: - Allwinner: SPDIF, A33 cpufreq, A33 Mali GPU - Aspeed: network, ipmi bt, gpio, pinmux - Broadcom: video encoder for raspberry pi, qspi, ethernet, sd/mmc - TI DaVinci: gpio, lcdc, usb, video-in, uart - TI Keystone 2: MSM RAM, power/reset, uart - Mediatek MT2701: clocks, iommu, spi, nand, adc, thermal - Marvell EBU: ethernet switch on Turris Omnia - NXP i.MX: otp ram, USB, wifi, bluetooth, spdif, spi, pmic, eeprom, mmc, nand - TI OMAP: - Qualcomm: coresight, gyro/accelerometer, hdmi - Renesas: pmic, soc-id - Rockchip: qos - Samsung: audio on Odroid-X - Socfpga: FPGA manager, i2c, led, can, watchdog, nand, power monitor - STi: video in/out - STM32: timer, pwm, i2c, rtc, add, i2s - NVIDIA Tegra: tpm - Uniphier: mmc/sd pinmux" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (380 commits) ARM: dts: armada-385-linksys: fix DSA compatible property ARM: dts: Fix typo in armada-xp-98dx4251 ARM: DTS: Fix register map for virt-capable GIC dt-bindings: arm,gic: Fix binding example for a virt-capable GIC ARM: dts: sun8i: sinlinx: Enable audio nodes ARM: dts: sun8i: parrot: Enable audio nodes ARM: dts: sun8i: Add audio codec, dai and card for A33 ARM: dts: Add EMAC AXI settings for Arria10 ARM: dts: am335x-chiliboard: Support charger ARM: dts: am335x-chiliboard: Support power button ARM: sun8i: dt: Add mali node dt-bindings: gpu: Add Mali Utgard bindings ARM: dts: stm32: Add I2C1 support for STM32429 eval board ARM: dts: stm32: Add I2C1 support for STM32F429 SoC ARM: dts: stm32: Use clock DT binding definition on stm32f429 family dt-bindings: mfd: stm32f4: Add missing binding definition dt-bindings: mfd: stm32f4: Fix STM32F4_X_CLOCK() macro ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco ARM: dts: stm32: add Timers driver for stm32f429 MCU ARM: dts: add the AB8500 sysclk to the device trees ...
2017-02-16clk: renesas: mstp: ensure register writes completeChris Brandt1-0/+6
When there is no status bit, it is possible for the clock enable/disable operation to have not completed by the time the driver code resumes execution. This is due to the fact that write operations are sometimes queued and delayed internally. Doing a read ensures the write operations has completed. Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to dtsi") Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-15clk: qcom: Do not drop device node twiceGuenter Roeck1-1/+0
of_find_node_by_name() drops the reference to a passed device node. It is not necessary to drop it again, and doing so may result in the device node being released prematurely. Cc: Rob Herring <robh@kernel.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Fixes: ee15faffef11 ("clk: qcom: common: Add API to register board clocks backwards compatibly") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-14clk: mvebu: adjust clock handling for the CP110 system controllerThomas Petazzoni1-2/+11
This commit: - makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP. - makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6) Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-10clk: mvebu: Expand mv98dx3236-core-clock supportChris Packham3-14/+181
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. Port code from the Marvell supplied Linux kernel to support different PLL frequencies and provide clock gating support. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-10clk: zte: add i2s clocks for zx296718Baoyou Xie1-0/+4
The i2s related clock support is missing from the existing zx296718 clock driver. This patch adds it, so that the upstream ZX I2S driver can work out. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-06clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()Wei Yongjun1-1/+1
PTR_ERR should access the value just tested by IS_ERR, otherwise the wrong error code will be returned. Fixes: 783ab76ae553 ("clk: sunxi-ng: Add A80 Display Engine CCU") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-06clk: sunxi-ng: select SUNXI_CCU_MULT for sun5iArnd Bergmann1-0/+1
We get a link error when CCU_MULT is not set with the newly added driver: drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.17+0x4): undefined reference to `ccu_mult_ops' drivers/clk/sunxi-ng/ccu-sun5i.o:(.data.__compound_literal.5+0x4): undefined reference to `ccu_mult_ops' Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-06clk: sunxi-ng: Check kzalloc() for errors and cleanup error pathStephen Boyd1-0/+15
This kzalloc() could fail. Let's bail out with -ENOMEM here instead of NULL dereferencing. That silences static checkers. We should also cleanup on the error path even though this function returning an error probably means the system won't boot. Cc: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03clk: tegra: Add BPMP clock driverThierry Reding3-0/+625
This driver uses the services provided by the BPMP firmware driver to implement a clock driver based on the MRQ_CLK request. This part of the BPMP ABI provides a means to enumerate and control clocks and should allow the driver to work on any chip that supports this ABI. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03Merge tag 'v4.11-rockchip-clk2' of ↵Stephen Boyd2-9/+16
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: "Non-critical fix for the pclk_edp divider on rk3399, one new clock-id and making niu (interconnect) clocks critical on rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running all the time when more users access particular clock subtrees." * tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3288: make all niu clocks critical clk: rockchip: use rk3288 vip_out clock ids clk: rockchip: add rk3288 vip_out clock id clk: rockchip: fix the incorrect pclk_edp div width for RK3399
2017-02-03clk: uniphier: add eMMC clock for LD11 and LD20 SoCsMasahiro Yamada1-0/+7
Add clock for the Cadence eMMC controller on LD11/LD20. For the other SoCs, the clock for the eMMC controller is included in the MIO/SD control block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03clk: uniphier: add NAND clock for all UniPhier SoCsMasahiro Yamada1-0/+14
Add clock line for the Denali NAND controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-03Merge tag 'sunxi-clk-for-4.11' of ↵Stephen Boyd27-58/+3748
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Pull Allwinner clock updates from Maxime Ripard: - Support for one new SoC, the V3s - Conversion of two old SoCs to the new framework, the old sun5i family and the A80 - A bunch of fixes * tag 'sunxi-clk-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (25 commits) ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU clk: sunxi-ng: Call divider_round_rate if we only have a single parent ARM: gr8: Convert to CCU ARM: sun5i: Convert to CCU clk: sunxi-ng: Add sun5i CCU driver clk: sunxi-ng: Implement global pre-divider clk: sunxi-ng: Implement multiplier maximum clk: sunxi-ng: mult: Fix minimum in round rate clk: sunxi-ng: Implement factors offsets clk: sunxi-ng: multiplier: Add fractional support clk: sunxi-ng: add support for V3s CCU dt-bindings: add device binding for the CCU of Allwinner V3s ...
2017-01-30PM / OPP: Update OPP users to put referenceViresh Kumar1-11/+6
This patch updates dev_pm_opp_find_freq_*() routines to get a reference to the OPPs returned by them. Also updates the users of dev_pm_opp_find_freq_*() routines to call dev_pm_opp_put() after they are done using the OPPs. As it is guaranteed the that OPPs wouldn't get freed while being used, the RCU read side locking present with the users isn't required anymore. Drop it as well. This patch also updates all users of devfreq_recommended_opp() which was returning an OPP received from the OPP core. Note that some of the OPP core routines have gained rcu_read_{lock|unlock}() calls, as those still use RCU specific APIs within them. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> [Devfreq] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2017-01-30clk: sunxi-ng: Add A80 Display Engine CCUChen-Yu Tsai3-0/+317
With the A80 SoC, Allwinner grouped and moved some subsystem specific clock controls to a separate address space, and possibly separate hardware block. One such subsystem is the display engine. The main clock control unit now only has 1 set of bus gate, dram gate, module clock, and reset control for the entire display subsystem. These feed into a secondary clock control unit, which has controls for each individual module of the display pipeline. This block is not documented in the user manual. Allwinner's kernel was used as the reference. Add support for the display engine clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: Add A80 USB CCUChen-Yu Tsai3-0/+170
Add support for the USB clock controls found on the A80. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: Add A80 CCUChen-Yu Tsai4-0/+1291
Add support for the main clock unit found in the A80. Some clocks were not documented in the released user manual, but were found in the official kernel from Allwinner. These include controls for the I2S, SPDIF, SATA, and eDP blocks. Note that on the A80, some subsystems have separate clock controllers downstream of the main clock unit. These include the MMC, USB, and display engine subsystems. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: Support separately grouped PLL lock status registerChen-Yu Tsai2-2/+9
On the Allwinner A80 SoC, the PLL lock status indicators are grouped together in a separate register, as opposed to being scattered in each PLL's configuration register. Add a flag to support this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENTChen-Yu Tsai1-1/+12
If the CLK_SET_RATE_PARENT flag is set, we want to try getting the closest parent rate. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flagChen-Yu Tsai1-0/+15
This patch adds support for the CLK_SET_RATE_NO_REPARENT flag to the mux determine_rate helper, based on examples from clk-composite and clk-mux. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-30clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividersChen-Yu Tsai1-3/+4
The determine_rate helper used ccu_mux_helper_adjust_parent_for_prediv() to adjust the parent_rate to account for pre-dividers, but then passed the pristine parent clock rate from clk_hw_get_rate() to the round() callback, thereby ignoring the pre-divider adjustment. In addition, it was saving the adjusted parent rate back into struct clk_rate_request. This patch fixes this by saving the pristine parent clock rate, and adding a copy that is adjusted and passed to the round() callback. The pristine copy, if it is the best solution, would be saved back to struct clk_rate_request. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-01-27clk: qcom: SDHCI enablement on Nexus 5X / 6PJeremy McNicoll1-0/+18
Add missing clock branch to enable onboard storage for msm899(2/4). Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27Merge tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung into ↵Stephen Boyd6-31/+66
clk-next Pull Samsung clk driver updates from Sylwester Nawrocki: - Exporting clock IDs for Exynos5433 SoC MIPI DSI DPHY - Exynos PLL code updates and overall minor clean-ups * tag 'clk-v4.11-samsung-2' of git://linuxtv.org/snawrocki/samsung: clk: samsung: mark s3c...._clk_sleep_init() as __init clk: samsung: Add enable/disable support for PLL35XX clocks clk: samsung: exynos5433: Correct typos in SoC name clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
2017-01-27Merge tag 'clk-renesas-for-v4.11-tag2' of ↵Stephen Boyd4-18/+144
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - Use CLK_IS_CRITICAL to handle critical clocks, - Add Reset Control Support for R-Car Gen2 and Gen3, and RZ/G1, - Add IIC-DVFS clocks for R-Car H3 and M3-W, - Minor cleanups. * tag 'clk-renesas-for-v4.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add IIC-DVFS clock clk: renesas: r8a7795: Add IIC-DVFS clock clk: renesas: cpg-mssr: Add support for reset control clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lock clk: renesas: cpg-mssr: Document suitability for RZ/G1 dt-bindings: clock: renesas: cpg-mssr: Document reset control support clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diff clk: renesas: mstp: Make INTC-SYS a critical clock clk: renesas: cpg-mssr: Migrate to CLK_IS_CRITICAL
2017-01-27clk: mvebu: support for 98DX3236 SoCChris Packham3-0/+70
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27clk: samsung: mark s3c...._clk_sleep_init() as __initMartin Kaiser4-8/+8
These functions are referencing s3c...._clk_regs[], which are marked as __initdata. When compiling with CONFIG_DEBUG_SECTION_MISMATCH=y, this produces warnings like WARNING: vmlinux.o(.text+0x198350): Section mismatch in reference from the function s3c2410_clk_sleep_init() to the (unknown reference) .init.data:(unknown) Mark the s3c...._clk_sleep_init() functions as __init in order to fix this. Fixes: ca2e90ac1809 ("clk: samsung: add clock controller driver for s3c2412") Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27clk: samsung: Add enable/disable support for PLL35XX clocksMarek Szyprowski1-7/+38
Some PLLs might be disabled by default after turning off and then on a power domain which they belongs to. To avoid configuring a disabled PLL, add proper code for handling PLL enable/disable. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27clk: samsung: exynos5433: Correct typos in SoC nameMarek Szyprowski1-14/+14
This patch fixes simple typos in Exynos5433 clocks driver. The SoC name was referred a few times as '5443' instead of '5433'. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL ratesMarek Szyprowski1-0/+2
Default clock configuration applied by the bootloader for TM2 and TM2e boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure such configuration for those boards with 'assigned-clock-*' properties, parameters for those two additional rates are needed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocksMarek Szyprowski1-2/+4
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-01-27clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPUMaxime Ripard1-1/+1
In order to achieve all the rates asked by the GPU, we might need to change the parent frequency. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-27clk: sunxi-ng: Call divider_round_rate if we only have a single parentMaxime Ripard1-0/+12
The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does. If we have a single parent, call divider_round_rate. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
2017-01-27clk: renesas: r8a7796: Add IIC-DVFS clockKhiem Nguyen1-0/+1
This patch adds DVFS clock for R8A7796 SoC. Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-27clk: renesas: r8a7795: Add IIC-DVFS clockKeita Kobayashi1-0/+1
This patch adds DVFS clock for R8A7795 SoC. Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-27clk: renesas: cpg-mssr: Add support for reset controlGeert Uytterhoeven1-0/+126
Add optional support for the Reset Control feature of the Renesas Clock Pulse Generator / Module Standby and Software Reset module on R-Car Gen2, R-Car Gen3, and RZ/G1 SoCs. This allows to reset SoC devices using the Reset Controller API. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2017-01-27clk: renesas: cpg-mssr: Rename cpg_mssr_priv.mstp_lockGeert Uytterhoeven1-5/+5
The spinlock is used to protect Read-Modify-Write register accesses, which won't be limited to SMSTPCR register accesses. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27clk: renesas: cpg-mssr: Document suitability for RZ/G1Geert Uytterhoeven1-1/+1
The Renesas CPG/MSSR driver is already in active use for RZ/G1 since commits c0b2d75d2a4bf6a3 ("clk: renesas: cpg-mssr: Add R8A7743 support") and 9127d54bb8947159 ("clk: renesas: cpg-mssr: Add R8A7745 support"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27clk: renesas: mstp: Reformat cpg_mstp_clock_register() for git diffGeert Uytterhoeven1-3/+3
As the function header of cpg_mstp_clock_register() is split in an unusual way, "git diff" gets confused when changes to the body of the function are made, and attributes them to the wrong function. Reformat the function header to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: x86: Add Atom PMC platform clocksIrina Tirdea2-0/+372
The BayTrail and CherryTrail platforms provide platform clocks through their Power Management Controller (PMC). The SoC supports up to 6 clocks (PMC_PLT_CLK[0..5]) with a frequency of either 19.2 MHz (PLL) or 25 MHz (XTAL) for BayTrail and a frequency of 19.2 MHz (XTAL) for CherryTrail. These clocks are available for general system use, where appropriate, and each have Control & Frequency register fields associated with them. Port from legacy by Pierre Bossart, integration in clock framework by Irina Tirdea Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: Make x86/ conditional on CONFIG_COMMON_CLKPierre-Louis Bossart1-0/+2
Fix Makefile for x86 support, dependency on CONFIG_COMMON_CLK was not explicit Fixes: 701190fd7419 ('clk: x86: add support for Lynxpoint LPSS clocks') Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: hisilicon: fix lock assignmentLeo Yan1-0/+1
In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96boards Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Fixes: 0aa0c95f743a ("clk: hisilicon: add common clock support") Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26Merge branch 'clk-ux500' into clk-nextStephen Boyd2-18/+29
* clk-ux500: clk: ux500: Convert ABx500 clocks to use OF probing clk: ux500: Add device tree bindings for ABx500 clocks clk: ux500: move AB8500 sysclk over to PRCMU clk driver
2017-01-26clk: ux500: Convert ABx500 clocks to use OF probingLinus Walleij1-10/+26
These clocks have been broken for a long time unfortunately, a hurdle of misc problems made them stop working at some point breaking USB and audio on Ux500. The platform as such and all "regular" clocks are migrated to OF/device tree, so let's migrate also this driver. With this patch and the corresponding DTS fixes, and a bunch of probe deferral fixes, audio starts working again on Ux500. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: ux500: move AB8500 sysclk over to PRCMU clk driverLinus Walleij2-8/+3
The AB8500 sysclk is just another PRCMU-controlled clock, there is no reason why it should be in the ABx500-controlled part of the clock implementation. Doing this and the corresponding device tree changes makes USB work on the Ux500 again. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: mediatek: Fix MT8135 dependenciesJean Delvare1-2/+2
The MT8135 is a 32-bit SoC, so only propose it on ARM architecture, not ARM64. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency") Cc: Andreas Färber <afaerber@suse.de> Acked-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: mediatek: Fix MT2701 dependenciesJean Delvare1-7/+8
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to be asked individually about each sub-driver. No means no. Additionally, this driver shouldn't be proposed at all on non-mediatek builds, unless build-testing. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Cc: Shunli Wang <shunli.wang@mediatek.com> Cc: Erin Lo <erin.lo@mediatek.com> Cc: Michael Turquette <mturquette@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: ti: divider: Add the table parsing to get the best divider valueKeerthy1-1/+30
Currently the divider selection logic blindly divides the parent_rate by the clk rate and gives the divider value for the divider clocks which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider table parsing to get the closest divider available in the table provided via Device tree. The code is pretty much taken from: drivers/clk/clk-divider.c. and used here to fix up the best divider selection logic. Signed-off-by: Keerthy <j-keerthy@ti.com> Reported-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-26clk: qcom: gdsc: Fix handling of hw control enable/disableRajendra Nayak1-13/+45
Once a gdsc is brought in and out of HW control, there is a power down and up cycle which can take upto 1us. Polling on the gdsc status immediately after the hw control enable/disable can mislead software/firmware to belive the gdsc is already either on or off, while its yet to complete the power cycle. To avoid this add a 1us delay post a enable/disable of HW control mode. Also after the HW control mode is disabled, poll on the status to check gdsc status reflects its 'on' before force disabling it in software. Reported-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Reviewed-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Tested-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Fixes: 904bb4f5c7de ("clk: qcom: gdsc: Add support for gdscs with HW control") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-06 16:01:34 +0000