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2017-06-09clk: samsung: exynos542x: Add EPLL rate tableSylwester Nawrocki1-2/+17
A specific clock rate table is added for EPLL so it is possible to set frequency of the EPLL output clock as multiple of various audio sampling rates. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09clk: samsung: Add missing exynos5420 audio related clocksSylwester Nawrocki1-3/+7
This patch adds missing definitions of mux clocks required for using EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09clk: samsung: Add enable/disable operation for PLL36XX clocksSylwester Nawrocki1-37/+50
The existing enable/disable ops for PLL35XX are made more generic and used also for PLL36XX. This fixes issues in the kernel with PLL36XX PLLs when the PLL has not been already enabled by bootloader. Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09clk: samsung: s5pv210-audss: Convert to the new clk_hw APIMarek Szyprowski1-25/+27
Clock providers should use the new struct clk_hw based API, so convert Samsung S5PV210 Audio Subsystem clock provider to the new approach. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-06-09clk: samsung: exynos-clkout: Convert to the new clk_hw APIMarek Szyprowski1-9/+9
Clock providers should use the new struct clk_hw based API, so convert Exynos CLKOUT clock provider to the new approach. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-09clk: samsung: exynos-audss: Convert to the new clk_hw APIMarek Szyprowski1-28/+29
Clock providers should use the new struct clk_hw based API, so convert Exynos Audio Subsystem clock provider to the new approach. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
2017-06-07clk: samsung: Convert common drivers to the new clk_hw APIMarek Szyprowski5-105/+92
Clock providers should use the new struct clk_hw based API, so convert Samsung clock providers and their helper functions to the new approach. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-07clk: samsung: Add local variable to match its purposeMarek Szyprowski1-4/+5
Add new variable to avoid using clk pointer for different purposes across the exynos_register_cpu_clock() function. This will help in future rewrite for the new clk_hw API. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-07clk: samsung: Remove dead codeMarek Szyprowski1-4/+0
samsung_clk_register_pll2550x() function is not used anymore, so remove its declaration. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-06-07clk: sunxi-ng: Move all clock types to a libraryStephen Boyd2-132/+22
We've run into kconfig missing dependency errors in the sunxi-ng code a couple times now. Each time the fix is to find the missing select statement and add it to the Kconfig entry for a particular SoC driver. Given that all this code is builtin (non-modular) we don't need to do this complicated dependency tracking in Kconfig. Instead we can move all the "library"ish code to be compiled as lib-y instead of obj-y, let the linker throw away unused code in the resulting vmlinux, and drop all the Kconfig stuff we use to track clock types. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [Maxime: added lib.a to obj-y, added the comment] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: a83t: Add support for A83T's PRCMChen-Yu Tsai1-0/+107
The A83T's PRCM has the same set of clocks and resets as the A64. However, a few dividers are different. And due to the lack of a low speed 32.768 kHz oscillator, a few of the clock parents are different. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83tArnd Bergmann1-0/+1
We get a link error when CCU_MULT is not set with the newly added driver: drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.1+0x4): undefined reference to `ccu_mult_ops' drivers/clk/sunxi-ng/ccu-sun8i-a83t.o:(.data.__compound_literal.3+0x4): undefined reference to `ccu_mult_ops' Fixes: 46b492116666 ("clk: sunxi-ng: Add driver for A83T CCU") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: a83t: Fix audio PLL divider offsetChen-Yu Tsai1-1/+1
The divider of the audio PLL has an offset of 1. Fix this in the driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: a83t: Fix PLL lock status register offsetChen-Yu Tsai1-1/+1
The offset for the PLL lock status register was incorrectly set to 0x208, which actually points to an unused register. The correct register offset is 0x20c. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: Add driver for A83T CCUChen-Yu Tsai4-0/+998
The A83T clock control unit is a hybrid of some new style clock designs from the A80, and old style layout from the other Allwinner SoCs. Like the A80, the SoC does not have a low speed 32.768 kHz oscillator. Unlike the A80, there is no clock input either. The only low speed clock available is the internal oscillator which runs at around 16 MHz, divided by 512, yielding a low speed clock around 31.250 kHz. Also, the MMC2 module clock supports switching to a "new timing" mode. This mode divides the clock output by half, and disables the CCU based clock delays. The MMC controller must be configure to the same mode, and then use its internal clock delays. This driver does not support runtime switching of the timing modes. Instead, the new timing mode is enforced at probe time. Consumers can check which mode is active by trying to get the current phase delay of the MMC2 phase clocks, which will return -ENOTSUPP if the new timing mode is active. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: Support multiple variable pre-dividersChen-Yu Tsai9-47/+54
On the A83T, the AHB1 clock has a shared pre-divider on the two PLL-PERIPH clock parents. To support such instances of shared pre-dividers, this patch extends the mux clock type to support multiple variable pre-dividers. As the pre-dividers are only used to calculate the rate, but do not participate in the factorization process, this is fairly straightforward. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR()Wei Yongjun1-1/+1
PTR_ERR should access the value just tested by IS_ERR, otherwise the wrong error code will be returned. Fixes: b0d9a4bd52bd ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: sun5i: Export video PLLsMaxime Ripard1-2/+4
The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: mux: Re-adjust parent rateMaxime Ripard1-5/+28
Currently, the parent rate given back to the clock framework in our request is the original parent rate we calculated before trying to round the rate of our clock. This works fine unless our clock also changes its parent rate, in which case we will simply ignore that change and still use the previous parent rate. Create a new function to re-adjust the parent rate to take the pre-dividers into account, and give that back to the clock framework. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: mux: Change pre-divider application function prototypeMaxime Ripard5-33/+28
The current function name is a bit confusing, and doesn't really allow to create an explicit function to reverse the operation. We also for now change the parent rate through a pointer, while we don't return anything. In order to be less confusing, and easier to use for downstream users, change the function name to something hopefully clearer, and return the adjusted rate instead of changing the pointer. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: mux: split out the pre-divider computation codeMaxime Ripard1-12/+20
The pre-divider retrieval code was merged into the function to apply the current pre-divider onto the parent clock rate so that we can use that adjusted value to do our factors computation. However, since we'll need to do the reverse operation, we need to split out that code into a function that will be shared. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENTMaxime Ripard1-13/+1
The current code only rely on the parent to change its rate in the case where CLK_SET_RATE_PARENT is set. However, some clock rates might be obtained only through a modification of the parent and the clock divider. Just rely on the round rate of the clocks to give us the best computation that might be achieved for a given rate. round_rate functions now need to honor CLK_SET_RATE_PARENT, but either the functions already do that if they modify the parent, or don't modify the praents at all. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: div: Switch to divider_round_rateMaxime Ripard1-23/+4
divider_round_rate_parent already evaluates changing the parent rate if CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's just use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: Pass the parent and a pointer to the clocks round rateMaxime Ripard6-18/+25
The clocks might need to modify their parent clocks. In order to make that possible, give them access to the parent clock being evaluated, and to a pointer to the parent rate so that they can modify it if needed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: divider: Make divider_round_rate take the parent clockMaxime Ripard1-9/+10
So far, divider_round_rate only considers the parent clock returned by clk_hw_get_parent. This works fine on clocks that have a single parents, this doesn't work on muxes, since we will only consider the first parent, while other parents may totally be able to provide a better combination. Clocks in that case cannot use divider_round_rate, so would have to come up with a very similar logic to work around it. Instead of having to do something like this, and duplicate that logic everywhere, create a divider_round_rate parent to allow caller to give an additional parameter for the parent clock to consider. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: explicitly include linux/spinlock.hTobias Klauser1-0/+1
ccu_reset.h and ccu_reset.c use spinlock_t and associated functions but rely on implict inclusion of linux/spinlock.h which means that changes in other headers could break the build. Thus, add an explicit include. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-07clk: sunxi-ng: add support for DE2 CCUIcenowy Zheng4-0/+294
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock management unit for its subunits, like the DE CCU in A80. Add a sunxi-ng style driver for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-06clk: imx7d: Fix the DDR PLL enable bitFabio Estevam1-1/+1
Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case. Fix it accordingly to avoid a kernel hang. Reported-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-05clk: at91: fix clk-generated compilationAlexandre Belloni1-0/+1
Fix missing } Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02clk: versatile: delete old RealView clock implementationLinus Walleij2-98/+0
The old RealView clock implementation is not used anymore (nothing in the kernel calls realview_clk_init()) as we have moved all clocks over to device tree. Delete it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02clk: bcm2835: Minimise clock jitter for PCM clockPhil Elwell1-5/+29
Fractional clock dividers generate accurate average frequencies but with jitter, particularly when the integer divisor is small. Introduce a new metric of clock accuracy to penalise clocks with a good average but worse jitter compared to clocks with an average which is no better but with lower jitter. The metric is the ideal rate minus the worse deviation from that ideal using the nearest integer divisors. Use this metric for parent selection for clocks requiring low jitter (currently just PCM). Signed-off-by: Phil Elwell <phil@raspberrypi.org> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02clk: bcm2835: Limit PCM clock to OSC and PLLD_PERPhil Elwell1-1/+26
Restrict clock sources for the PCM peripheral to the oscillator and PLLD_PER because other source may have varying rates or be switched off. Prevent other sources from being selected by replacing their names in the list of potential parents with dummy entries (entry index is significant). Signed-off-by: Phil Elwell <phil@raspberrypi.org> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02clk: bcm2835: Correct the prediv logicPhil Elwell1-1/+3
If a clock has the prediv flag set, both the integer and fractional parts must be scaled when calculating the resulting frequency. Signed-off-by: Phil Elwell <phil@raspberrypi.org> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02Merge branch 'clk-bulk-get' into clk-nextStephen Boyd3-1/+194
* clk-bulk-get: clk: add managed version of clk_bulk_get clk: add clk_bulk_get accessories
2017-06-02clk: add managed version of clk_bulk_getDong Aisheng1-0/+36
This patch introduces the managed version of clk_bulk_get. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Mark Brown <broonie@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Anson Huang <anson.huang@nxp.com> Cc: Robin Gong <yibin.gong@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: Octavian Purdila <octavian.purdila@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02clk: add clk_bulk_get accessoriesDong Aisheng2-1/+158
These helper function allows drivers to get several clk consumers in one operation. If any of the clk cannot be acquired then any clks that were got will be put before returning to the caller. This can relieve the driver owners' life who needs to handle many clocks, as well as each clock error reporting. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Mark Brown <broonie@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Anson Huang <anson.huang@nxp.com> Cc: Robin Gong <yibin.gong@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: Octavian Purdila <octavian.purdila@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02clk: meson-gxbb: Add const to some parent name arraysStephen Boyd1-3/+3
These can be marked as const * const. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02Merge tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd3-74/+73
clk-next Pull Amlogic clock driver updates from Jerome Brunet: * Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks * tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson: clk: meson-gxbb: Add EE 32K Clock for CEC clk: gxbb: remove CLK_IGNORE_UNUSED from clk81 clk: meson: meson8b: mark clk81 as critical clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
2017-06-02clk: palmas: undo preparation of a clock source.Arvind Yadav1-0/+1
Undo preparation of a clock source, if palmas_clks_init_configure is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-02clk: rockchip: mark some special clk as critical on rk3368Elaine Zhang1-1/+4
The jtag clk no driver to handle them. But this clk need enable,so make it as critical. The ddrphy/ddrupctl clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: mark noc and some special clk as critical on rk3288Elaine Zhang1-4/+10
The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them. But this clks need enable,so make it as ignore_unused for now. The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: mark noc and some special clk as critical on rk3228Elaine Zhang1-1/+29
The jtag/bus/peri/initmem/rom/stimer/phy clks no driver to handle them. But this clks need enable,so make it as critical. The ddrupctl/ddrmon/ddrphy clks no driver to handle them, Chip design requirements for these clock to always on, The hclk_otg_pmu is Chip design defect, must be always on, The new document will update the description of this clock. All these non-noc/non-arbi clocks,IC suggest always on, Because it's have some order limitation, between the NOC clock switch and bus IDLE(or pd on/off). The software is not very good to solve this constraint. Always on these clocks, has no effect on the system power consumption. The new document will update the description of these clock. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036Elaine Zhang1-0/+1
No driver to handle this clk yet, but chip design requiress for this clock supplying the ddr controller to be always on. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: add clock controller for rk3128Elaine Zhang2-0/+613
Add the clock tree definition for the new rk3128 SoC. And it also applies to the RK3126 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: export more rk3228 clocks idsElaine Zhang1-46/+46
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/ VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02clk: rockchip: add ids for rk3399 testclks used for camera handlingEddie Cai1-2/+2
clk_testout1 and clk_testout2 are used for camera handling, so add their ids. Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-06-02Merge tag 'clk-renesas-for-v4.13-tag1' of ↵Michael Turquette14-72/+1319
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next clk: renesas: Updates for v4.13 - Add more module clocks for R-Car H3 ES2.0 and M3-W, - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support for module resets, which are not supported by the existing driver, - Rework Kconfig and Makefile logic, - Small fixes and cleanups.
2017-06-01clk: mvebu: cp110: make failure labels more meaningfulGregory CLEMENT1-10/+10
In preparation to the addition of a new clock, rename the goto labels used to handle the failure cases using a name related to the failure cause. This will allow to insert additional failing cases without renaming all the labels. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-01clk: Fix __set_clk_rates error print-stringBryan O'Donoghue1-1/+1
When failing to set a clock the printout emitted is incorrect. "u32 rate" is formatted as %d and should be %u whereas "unsigned long clk_set_rate()" is formatted as %ld and should be %lu as per Documentation/printk-formats.txt. Fixes: 2885c3b2a3da ("clk: Show correct information when fail to set clock rate") Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-01clk: scpi: fix return type of __scpi_dvfs_round_rateSudeep Holla1-3/+3
The frequencies above the maximum value of signed integer(i.e. 2^31 -1) will overflow with the current code. This patch fixes the return type of __scpi_dvfs_round_rate from 'int' to 'unsigned long'. Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)") Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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