summaryrefslogtreecommitdiffstats
path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2019-02-15clk: ti: move clk_hw_omap list handling under generic part of the driverTero Kristo3-39/+69
2019-02-13Merge tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/k...Stephen Boyd2-3/+3
2019-02-13clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl2-14/+14
2019-02-13clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong4-1/+491
2019-02-06clk: clk-st: avoid clkdev lookup leak at removeMatti Vaittinen1-1/+2
2019-02-06clk: clk-max77686: Clean clkdev lookup leak and use devmMatti Vaittinen1-22/+6
2019-02-06clkdev: add managed clkdev lookup registrationMatti Vaittinen1-23/+88
2019-02-06clk: Add (devm_)clk_get_optional() functionsPhil Edworthy1-0/+11
2019-02-06clk: Add comment about __of_clk_get_by_name() error valuesPhil Edworthy1-0/+6
2019-02-06clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210Peter De Schrijver2-1/+6
2019-02-06clk: tegra: dfll: add CVB tables for Tegra210Joseph Lo2-0/+427
2019-02-06clk: tegra: dfll: round down voltages based on alignmentJoseph Lo1-8/+13
2019-02-06clk: tegra: dfll: support PWM regulator controlJoseph Lo1-67/+377
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo4-14/+59
2019-02-06clk: tegra: dfll: registration for multiple SoCsPeter De Schrijver1-11/+34
2019-02-05clk: ingenic: jz4740: Fix gating of UDC clockPaul Cercueil1-1/+1
2019-02-05clk: mediatek: update clock driver of MT2712Weiyi Lu1-2/+6
2019-02-05clk: renesas: r8a774c0: Add TMU clockBiju Das1-0/+5
2019-02-05clk: renesas: r8a77980: Add RPC clocksSergei Shtylyov1-0/+8
2019-02-05clk: renesas: rcar-gen3: Add RPC clocksSergei Shtylyov2-0/+105
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet7-176/+313
2019-02-04clk: meson: g12a: add peripheral clock controllerJian Hu5-2/+2594
2019-02-04clk: meson: pll: update driver for the g12aJerome Brunet2-59/+154
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet29-281/+465
2019-02-02clk: meson: axg-audio does not require sysconJerome Brunet1-1/+1
2019-02-02clk: meson: use CONFIG_ARCH_MESON to enter meson clk directoryJerome Brunet1-1/+1
2019-02-02clk: export some clk_hw function symbols for module driversJerome Brunet1-0/+3
2019-02-01clk: samsung: exynos5433: Add selected IMEM clocksKamil Konieczny1-0/+32
2019-02-01clk: samsung: exynos5433: Fix name typo in sssxKamil Konieczny1-1/+1
2019-02-01clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocksKamil Konieczny1-2/+2
2019-01-28clk: sunxi: A31: Fix wrong AHB gate numberAndre Przywara1-2/+2
2019-01-25clk: renesas: rcar-gen3: Add spinlockSergei Shtylyov1-0/+8
2019-01-25clk: renesas: rcar-gen3: Factor out cpg_reg_modify()Sergei Shtylyov1-18/+20
2019-01-25clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating itChen-Yu Tsai1-1/+1
2019-01-24clk: samsung: fix typoMatteo Croce1-1/+1
2019-01-24clk: qcom: gcc: Use active only source for CPUSS clocksTaniya Das1-4/+10
2019-01-24clk: imx: imx7ulp: use struct_size() in kzalloc()Gustavo A. R. Silva1-8/+8
2019-01-24clk: socfpga: Don't have get_parent for single parent opsStephen Boyd1-9/+13
2019-01-24clk: ti: Fix error handling in ti_clk_parse_divider_data()Dan Carpenter1-1/+10
2019-01-24clk: imx: Fix fractional clock set rate computationAbel Vesa1-2/+3
2019-01-24clk: Remove global clk traversal on fetch parent indexDerek Basehore1-2/+12
2019-01-24Revert "clk: mmp2: add SP clock"Lubomir Rintel1-4/+0
2019-01-24clk: renesas: r8a774c0: Correct parent clock of DUGeert Uytterhoeven1-2/+2
2019-01-22clk: sunxi-ng: v3s: Fix TCON reset de-assert bitPaul Kocialkowski1-1/+1
2019-01-21clk: renesas: r8a774a1: Add missing CANFD clockFabrizio Castro1-0/+2
2019-01-21clk: renesas: r8a774c0: Add missing CANFD clockFabrizio Castro1-0/+4
2019-01-18clk: meson: ao-clkc: claim clock controller input clocks from DTJerome Brunet4-14/+82
2019-01-18clk: meson: axg: claim clock controller input clock from DTJerome Brunet1-8/+19
2019-01-18clk: meson: gxbb: claim clock controller input clock from DTJerome Brunet1-13/+24
2019-01-15clk: socfpga: stratix10: fix naming convention for the fixed-clocksDinh Nguyen1-10/+10