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2020-03-12clk: tegra: Remove tegra_pmc_clk_init along with clk idsSowjanya Komatineni9-201/+19
Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2, clk_out_3 and 32KHz blink output in tegra_pmc_init() which does direct PMC register access during clk_ops and these PMC register read and write access will not happen when PMC is in secure mode. Any direct PMC register access from non-secure world will not go through. All the PMC clocks are moved to Tegra PMC driver with PMC as a clock provider. This patch removes tegra_pmc_clk_init along with corresponding clk ids from Tegra clock driver. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Remove CLK_M_DIV fixed clocksSowjanya Komatineni6-45/+0
Tegra has no CLK_M_DIV2 and CLK_M_DIV4 clocks and instead it has OSC_DIV2 and OSC_DIV4 clocks from OSC pads which are the possible parents of PMC clocks for Tegra30 through Tegra210. Tegra PMC clock parents are changed to use OSC_DIV clocks. So, this patch removes CLK_M_DIV fixed clocks Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Fix Tegra PMC clock out parentsSowjanya Komatineni1-6/+6
Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3 supported parents are osc, osc_div2, osc_div4 and extern clock. Clock driver is using incorrect parents clk_m, clk_m_div2, clk_m_div4 for PMC clocks. This patch fixes this. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Add Tegra OSC to clock lookupSowjanya Komatineni6-0/+14
OSC is one of the parent for Tegra PMC clocks clk_out_1, clk_out_2, and clk_out_3. This patch adds Tegra OSC to clock lookup. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-12clk: tegra: Add support for OSC_DIV fixed clocksSowjanya Komatineni6-0/+34
Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks from the OSC pads. This patch adds support for these clocks. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-11clk: imx8mq: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11clk: imx8mp: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11clk: imx8mm: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-11clk: imx8mn: A53 core clock no need to be criticalAnson Huang1-4/+4
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: pllv4: use prepare/unpreparePeng Fan1-6/+6
It is not good to use enable/disable for PLLv4 which needs time to lock, because enable/disable is expected to be able run in interrupt context. So use prepare/unprepare. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: pfdv2: determine best parent ratePeng Fan1-17/+33
pfdv2 is only used in i.MX7ULP. To get best pfd output, the i.MX7ULP Datasheet defines two best PLL rate and pfd frac. Per Datasheel All PLLs on i.MX 7ULP either have VCO base frequency of 480 MHz or 528 MHz. So when determine best rate, we also determine best parent rate which could match the requirement. For some reason the current parent might not be 480MHz or 528MHz, so we still take current parent rate as a choice. And we also enable flag CLK_SET_RATE_PARENT to let parent rate to be configured. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: pfdv2: switch to use determine_ratePeng Fan1-6/+9
Per clk_ops, compared with round_rate, determine_rate could optionally support the parent clock that should be used to provide the clock rate. In this patch, the parent clock is just parent->rate as round_rate. The following patch will calculate the best parent clock. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-10clk: imx: Fix division by zero warning on pfdv2Anson Huang1-0/+6
Fix below division by zero warning: [ 3.176443] Division by zero in kernel. [ 3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124 [ 3.191817] Hardware name: Freescale i.MX7ULP (Device Tree) [ 3.197821] Workqueue: events dbs_work_handler [ 3.202849] [<c01127d8>] (unwind_backtrace) from [<c010cd80>] (show_stack+0x10/0x14) [ 3.211058] [<c010cd80>] (show_stack) from [<c0c77e68>] (dump_stack+0xd8/0x110) [ 3.218820] [<c0c77e68>] (dump_stack) from [<c0c753c0>] (Ldiv0_64+0x8/0x18) [ 3.226263] [<c0c753c0>] (Ldiv0_64) from [<c05984b4>] (clk_pfdv2_set_rate+0x54/0xac) [ 3.234487] [<c05984b4>] (clk_pfdv2_set_rate) from [<c059192c>] (clk_change_rate+0x1a4/0x698) [ 3.243468] [<c059192c>] (clk_change_rate) from [<c0591a08>] (clk_change_rate+0x280/0x698) [ 3.252180] [<c0591a08>] (clk_change_rate) from [<c0591fc0>] (clk_core_set_rate_nolock+0x1a0/0x278) [ 3.261679] [<c0591fc0>] (clk_core_set_rate_nolock) from [<c05920c8>] (clk_set_rate+0x30/0x64) [ 3.270743] [<c05920c8>] (clk_set_rate) from [<c089cb88>] (imx7ulp_set_target+0x184/0x2a4) [ 3.279501] [<c089cb88>] (imx7ulp_set_target) from [<c0896358>] (__cpufreq_driver_target+0x188/0x514) [ 3.289196] [<c0896358>] (__cpufreq_driver_target) from [<c0899b0c>] (od_dbs_update+0x130/0x15c) [ 3.298438] [<c0899b0c>] (od_dbs_update) from [<c089a5d0>] (dbs_work_handler+0x2c/0x5c) [ 3.306914] [<c089a5d0>] (dbs_work_handler) from [<c0156858>] (process_one_work+0x2ac/0x704) [ 3.315826] [<c0156858>] (process_one_work) from [<c0156cdc>] (worker_thread+0x2c/0x574) [ 3.324404] [<c0156cdc>] (worker_thread) from [<c015cfe8>] (kthread+0x134/0x148) [ 3.332278] [<c015cfe8>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) [ 3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8) [ 3.345314] 5fa0: 00000000 00000000 00000000 00000000 [ 3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-03-09clk: qcom: gcc: Add global clock controller driver for SM8250Taniya Das3-0/+3698
Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-6-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-09clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLsTaniya Das2-0/+205
Add programming sequence support for managing the Lucid PLLs. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-4-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-09clk: qcom: clk-alpha-pll: Refactor trion PLLTaniya Das1-27/+6
Remove duplicate function for calculating the round rate of PLL and also update the trion pll ops to use the common function. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-3-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-09clk: qcom: clk-alpha-pll: Use common names for definesTaniya Das1-23/+17
The PLL run and standby modes are similar across the PLLs, thus rename them to common names and update the use of these. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200224045003.3783838-2-vkoul@kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-09clk: qcom: smd: Add support for MSM8976 rpm clocksAngeloGioacchino Del Regno1-0/+50
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8976, MSM8956 (and APQ variants) for clients to vote on. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lkml.kernel.org/r/20191031112951.35850-2-kholk11@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-09clk: qcom: clk-rpmh: Wait for completion when enabling clocksMike Tipton1-2/+13
The current implementation always uses rpmh_write_async, which doesn't wait for completion. That's fine for disable requests since there's no immediate need for the clocks and they can be disabled in the background. However, for enable requests we need to ensure the clocks are actually enabled before returning to the client. Otherwise, clients can end up accessing their HW before the necessary clocks are enabled, which can lead to bus errors. Use the synchronous version of this API (rpmh_write) for enable requests in the active set to ensure completion. Completion isn't required for sleep/wake sets, since they don't take effect until after we enter sleep. All rpmh requests are automatically flushed prior to entering sleep. Fixes: 9c7e47025a6b ("clk: qcom: clk-rpmh: Add QCOM RPMh clock driver") Signed-off-by: Mike Tipton <mdtipton@codeaurora.org> Link: https://lkml.kernel.org/r/20200215021232.1149-1-mdtipton@codeaurora.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> [sboyd@kernel.org: Reorg code a bit for readability, rename to 'wait' to make local variable not conflict with completion.h mechanism] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-09clk: renesas: rcar-usb2-clock-sel: Add reset_controlYoshihiro Shimoda2-1/+15
This hardware needs to deassert resets of both host and peripheral. So, this patch adds reset control. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1583304137-28482-5-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-09clk: renesas: rcar-usb2-clock-sel: Add multiple clocks managementYoshihiro Shimoda1-2/+25
This hardware needs to enable clocks of both host and peripheral. So, this patch adds multiple clocks management. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1583304137-28482-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-03-06clk: rockchip: fix mmc get phaseJerome Brunet1-2/+2
If the mmc clock has no rate, it can be assumed to be constant. In such case, there is no measurable phase shift. Just return 0 in this case instead of returning an error. Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration") Tested-by: Markus Reichl <m.reichl@fivetechno.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20200303192956.64410-1-jbrunet@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-28clk: Fix phase init checkMaxime Ripard1-2/+4
Commit 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration") introduced a check on error values at the time the clock is registered to bail out when such an error occurs. However, it doesn't check whether the returned value is positive which will happen if the driver returns a non-zero phase. Since a phase is usually a non-zero positive number this ends up returning something that isn't 0 to the caller of __clk_core_init(), making most clks fail to register if they implement a phase clk op and return anything besides 0 for the phase. Fix this by returning the error if phase is less than zero or just return zero if the phase is a positive number. Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lkml.kernel.org/r/20200225134248.919889-1-maxime@cerno.tech Reported-by: "kernelci.org bot" <bot@kernelci.org> [sboyd@kernel.org: Reword commit text to provide clarity] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-24clk: imx: clk-sscg-pll: Drop unnecessary initializationAnson Huang1-7/+7
No need to initialize 'ret' in many functions, as it will get the return value from function call, so remove the initializtion of 'ret'. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24clk: imx: pll14xx: Return error if pll type is invalidAnson Huang1-0/+2
When pll type is invalid, ONLY output error message is NOT enough, should return error immediately. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24clk: imx: imx8mp: fix a53 cpu clockPeng Fan1-4/+12
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24clk: imx: imx8mn: fix a53 cpu clockPeng Fan1-4/+12
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clk. Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24clk: imx: imx8mm: fix a53 cpu clockPeng Fan1-4/+12
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clock Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24clk: imx: imx8mq: fix a53 cpu clockPeng Fan1-4/+12
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which violates the CCM. There is a CORE_SEL slice before A53 core, we need to configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clock Fixes: db27e40b27f1 ("clk: imx8mq: Add the missing ARM clock") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-24clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clockAnson Huang1-2/+2
On i.MX8MP, internal HDMI 27M clock is actually 24MHz, so rename the IMX8MP_CLK_HDMI_27M to IMX8MP_CLK_HDMI_24M. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-21clk: renesas: Remove use of ARCH_R8A7795Geert Uytterhoeven1-1/+1
CONFIG_ARCH_R8A7795 was split in CONFIG_ARCH_R8A77950 and CONFIG_ARCH_R8A77951 in commit b925adfceb529389 ("soc: renesas: Add ARCH_R8A7795[01] for existing R-Car H3"), so its users can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200218112525.5834-1-geert+renesas@glider.be
2020-02-21clk: meson: meson8b: set audio output clock hierarchyMartin Blumenstingl1-8/+13
The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to operate. Reflect this hierarchy in the clock tree. Fixes: e31a1900c1ff73 ("meson: clk: Add support for clock gates") Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-02-19clk: meson: g12a: add support for the SPICC SCLK Source clocksNeil Armstrong2-1/+134
This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC controller to provide a more complete range of frequencies instead of the SPICC internal divider over Xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-02-19clk: imx8mn: Remove unused includesAnson Huang1-2/+0
There is nothing in use from init.h/of.h, remove them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-19clk: imx8mm: Remove unused includesAnson Huang1-2/+0
There is nothing in use from init.h/of.h, remove them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-19clk: imx8mp: Include slab.h instead of clkdev.hAnson Huang1-1/+1
slab.h is necessary and included indirectly by clkdev.h, actually, there is nothing in use from clkdev.h, so just include slab.h instead of clkdev.h. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-18clk: at91: move sam9x60's PLL register offsets to PMC headerClaudiu Beznea1-54/+37
Move SAM9X60's PLL register offsets to PMC header so that the definitions would also be available from arch/arm/mach-at91/pm_suspend.S. This is necessary to disable/enable PLLA for SAM9X60 on suspend/resume. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1579522208-19523-7-git-send-email-claudiu.beznea@microchip.com
2020-02-17clk: imx8mp: Add missing of_node_put()Anson Huang1-0/+1
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx8mn: Add missing of_node_put()Anson Huang1-0/+1
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx8mm: Add missing of_node_put()Anson Huang1-0/+1
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx8mq: Add missing of_node_put()Anson Huang1-0/+1
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx6sl: Add missing of_node_put()Anson Huang1-0/+1
After finishing using device node got from of_find_compatible_node(), of_node_put() needs to be called. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx7ulp: Include clk-provider.h instead of clk.hAnson Huang1-1/+1
The i.MX7ULP clock driver is provider, NOT consumer, so clk-provider.h should be used instead of clk.h. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx: drop redundant initializationAnson Huang4-6/+6
No need to initialize flags as 0, remove the initialization. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx: Include clk-provider.h instead of clk.h for i.MX8M SoCs clock driverAnson Huang3-3/+3
The i.MX8M SoCs clock driver are provider, NOT consumer, so clk-provider.h should be used instead of clk.h. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx8mm: Add CLKO2 supportFabio Estevam1-0/+3
Add CLKO2 support, which is useful for debugging purposes. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-17clk: imx8mm: Fix the CLKO1 source select listFabio Estevam1-2/+2
The CLKO1 clock source select list is the following as per the i.MX8MM Reference Manual (put in increasing order): 000 - 24M_REF_CLK 001 - SYSTEM_PLL1_CLK 010 - None 011 - SYSTEM_PLL1_DIV4 100 - AUDIO_PLL2_CLK 101 - SYSTEM_PLL2_DIV2 110 - VPU_PLL_CLK 111 - SYSTEM_PLL1_DIV10 Fix it accordingly. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-14clk: imx: imx8mn: use imx8m_clk_hw_composite_corePeng Fan1-8/+11
Use imx8m_clk_hw_composite_core to simplify code. Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-14clk: imx: imx8mm: use imx8m_clk_hw_composite_corePeng Fan1-14/+21
Use imx8m_clk_hw_composite_core to simplify code. Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-02-14clk: imx: imx8mq: use imx8m_clk_hw_composite_corePeng Fan1-15/+19
Use imx8m_clk_hw_composite_core to simplify code. Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-24 14:46:25 +0000