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path: root/drivers/clk
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2013-04-08Merge tag 'omap-for-v3.10/fixes-non-critical-signed' of git://git.kernel.org/...Arnd Bergmann3-3/+1
2013-04-08clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}Tushar Behera1-4/+4
2013-04-08clk: exynos4: export clocks required for fimc-isSylwester Nawrocki1-7/+13
2013-04-08clk: samsung: Fix compilation errorSachin Kamat1-0/+2
2013-04-08ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>Linus Walleij1-1/+0
2013-04-08clk: ux500: pass clock base adresses in init callLinus Walleij1-71/+71
2013-04-04clk: tegra: fix enum tegra114_clk to match bindingStephen Warren1-1/+1
2013-04-04clk: tegra: Remove forced clk_enable of uartdPeter De Schrijver1-1/+1
2013-04-04clk: tegra: devicetree match for nvidia,tegra114-carPeter De Schrijver2-0/+7
2013-04-04clk: tegra: Implement clocks for Tegra114Peter De Schrijver2-0/+2086
2013-04-04clk: tegra: Workaround for Tegra114 MSENC problemPeter De Schrijver2-0/+11
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver4-10/+14
2013-04-04clk: tegra: Add new fields and PLL types for Tegra114Peter De Schrijver2-1/+888
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver4-25/+25
2013-04-04clk: tegra: Add PLL post divider tablePeter De Schrijver4-6/+59
2013-04-04clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLEPeter De Schrijver2-0/+7
2013-04-04clk: tegra: Add TEGRA_PLL_BYPASS flagPeter De Schrijver2-4/+10
2013-04-04clk: tegra: Refactor PLL programming codePeter De Schrijver4-293/+356
2013-04-04clk: tegra: provide dummy cpu car opsPeter De Schrijver1-1/+2
2013-04-04clk: tegra: defer application of init tableStephen Warren4-2/+25
2013-04-04clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad2-2/+2
2013-04-04clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding2-0/+4
2013-04-04clk: tegra: Export peripheral reset functionsThierry Reding1-0/+3
2013-04-04clk: tegra: Fix periph_clk_to_bit macroYen Lin1-1/+1
2013-04-04Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into for-...Stephen Warren16-123/+1422
2013-04-04Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren1-34/+2
2013-04-04clk: sunxi: drop an unnecesary kmallocEmilio López1-1/+1
2013-04-04clk: sunxi: drop CLK_IGNORE_UNUSEDEmilio López1-4/+4
2013-04-04clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gatesEmilio López1-0/+88
2013-04-04clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala1-1/+9
2013-04-04clk: exynos4: Add support for SoC-specific register save listTomasz Figa5-8/+39
2013-04-04clk: exynos4: Add missing registers to suspend save listTomasz Figa1-0/+33
2013-04-04clk: exynos4: Remove E4X12 prefix from SRC_DMC registerTomasz Figa1-2/+2
2013-04-04clk: exynos4: Add E4210 prefix to GATE_IP_PERIR registerTomasz Figa1-8/+8
2013-04-04clk: exynos4: Add E4210 prefix to LCD1 clock registersTomasz Figa1-11/+11
2013-04-04clk: exynos4: Remove SoC-specific registers from save listTomasz Figa1-16/+0
2013-04-04clk: exynos4: Use SRC_MASK_PERIL{0,1} definitionsTomasz Figa1-11/+19
2013-04-04clk: exynos4: Define {E,V}PLL registersTomasz Figa1-4/+12
2013-04-04clk: exynos4: Add missing mout_sata on Exynos4210Tomasz Figa1-0/+1
2013-04-04clk: exynos4: Add missing CMU_TOP and ISP clocksAndrzej Hajda1-3/+107
2013-04-04clk: exynos4: Add G3D clocksTomasz Figa1-8/+14
2013-04-04clk: exynos4: Add camera related clock definitionsSylwester Nawrocki1-17/+33
2013-04-04clk: exynos4: Export mout_core clock of Exynos4210Tomasz Figa1-1/+2
2013-04-04clk: samsung: Remove unimplemented ops for pllTomasz Figa1-80/+0
2013-04-04clk: exynos4: Export clocks used by exynos cpufreq driversLukasz Majewski1-3/+5
2013-04-04clk: exynos4: Move dac and mixer to Exynos4210-specific clocksTomasz Figa1-2/+2
2013-04-04clk: exynos4: Export sclk_pcm0Tomasz Figa1-2/+2
2013-04-04clk: exynos4: Add missing sclk_audio0 clockTomasz Figa1-0/+2
2013-04-04clk: exynos4: Add missing mout_mipihsi clockTomasz Figa1-0/+1
2013-04-04clk: exynos4: Use mout_mpll_user_* on Exynos4x12Tomasz Figa1-61/+111