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2014-05-05ARM: AM43xx: clk: Change the cpts ref clock source to dpll_core_m5 clkGeorge Cherian1-0/+16
cpsw_cpts_rft_clk has got the choice of 3 clocksources -dpll_core_m4_ck -dpll_core_m5_ck -dpll_disp_m2_ck By default dpll_core_m4_ck is selected, witn this as clock source the CPTS doesnot work properly. It gives clockcheck errors while running PTP. clockcheck: clock jumped backward or running slower than expected! By selecting dpll_core_m5_ck as the clocksource fixes this issue. In AM335x dpll_core_m5_ck is the default clocksource. Signed-off-by: George Cherian <george.cherian@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-04-07Merge tag 'mfd-for-linus-3.15' of ↵Linus Torvalds1-4/+0
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "Changes to existing drivers: - Use of managed resources - omap, twl4030, ti_am335x_tscadc - Advanced error handling - omap - Rework clk management - omap - Device Tree (re-)work - tc3589x, pm8921, da9055, sec - IRC management overhaul and !BROKEN - pm8921 - Convert to regmap - ssbi, pm8921 - Use simple power-management ops - ucb1x00 - Include file clean-up - adp5520, cs5535, janz, lpc_ich, - lpc_sch, max14577, mcp-sa11x0, pcf50633-adc, rc5t583, rdc321x-southbridge, retu, smsc-ece1099, ti-ssp, ti_am335x_tscadc, tps65912, vexpress-config, wm8350, ywm8350 - Various bug fixes across the subsystem - NULL/invalid pointer dereference prevention - Resource leak mitigation, - Variable used initialised - Staticise various containers - Enforce return value checks New drivers/supported devices: - Add support for s2mps14 and s2mpa01 to sec - Add support for da9063 (v5) to da9063 - Add support for atom-c2000 to gpio-ich - Add support for come-{mbt10,cbt6,chl6} to kempld - Add support for da9053 to da9052 - Add support for itco-wdt (v3) and baytrail to lpc_ich - Add new drivers for tps65218, rtsx_usb, bcm590xx (Re-)moved drivers: - twl4030 ==> drivers/iio - ti-ssp ==> /dev/null" * tag 'mfd-for-linus-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (103 commits) mfd: wm5110: Correct default for HEADPHONE_DETECT_1 mfd: arizona: Correct small errors in the DT binding documentation mfd: arizona: Mark DSP clocking register as volatile mfd: devicetree: bindings: Add pm8xxx RTC description mfd: kempld-core: Fix potential hang-up during boot mfd: sec-core: Fix uninitialized 'regmap_rtc' on S2MPA01 mfd: tps65910: Fix regmap_irq_chip_data leak on mfd_add_devices fail mfd: tps65910: Fix possible invalid pointer dereference on regmap_add_irq_chip fail mfd: sec-core: Fix I2C dummy device resource leak on probe failure mfd: sec-core: Add of_compatible strings for clock MFD cells mfd: Remove obsolete ti-ssp driver Documentation: mfd: s2mps11: Describe S5M8767 and S2MPS14 clocks mfd: bcm590xx: Fix type argument for module device table mfd: lpc_ich: Add support for Intel Bay Trail SoC mfd: lpc_ich: Add support for NM10 GPIO mfd: lpc_ich: Change Avoton to iTCO v3 watchdog: iTCO_wdt: Add support for v3 silicon mfd: lpc_ich: Add support for iTCO v3 mfd: lpc_ich: Remove lpc_ich_cfg struct use mfd: lpc_ich: Only configure watchdog or GPIO when present ...
2014-04-05Merge tag 'clk-for-linus-3.15' of ↵Linus Torvalds48-698/+5161
git://git.linaro.org/people/mike.turquette/linux Pull clock framework changes from Mike Turquette: "The clock framework changes for 3.15 look similar to past pull requests. Mostly clock driver updates, more Device Tree support in the form of common functions useful across platforms and a handful of features and fixes to the framework core" * tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: shmobile: fix setting paretn clock rate clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1 clk: Fix minor errors in of_clk_init() function comments clk: reverse default clk provider initialization order in of_clk_init() clk: sirf: update copyright years to 2014 clk: mmp: try to use closer one when do round rate clk: mmp: fix the wrong calculation formula clk: mmp: fix wrong mask when calculate denominator clk: st: Adds quadfs clock binding clk: st: Adds clockgen-vcc and clockgen-mux clock binding clk: st: Adds clockgen clock binding clk: st: Adds divmux and prediv clock binding clk: st: Support for A9 MUX clocks clk: st: Support for ClockGenA9/DDR/GPU clk: st: Support for QUADFS inside ClockGenB/C/D/E/F clk: st: Support for VCC-mux and MUX clocks clk: st: Support for PLLs inside ClockGenA(s) clk: st: Support for DIVMUX and PreDiv Clocks clk: support hardware-specific debugfs entries clk: s2mps11: Use of_get_child_by_name ...
2014-04-05Merge tag 'tags/cleanup2-3.15' of ↵Linus Torvalds3-30/+67
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late cleanups from Arnd Bergmann: "These could not be part of the first cleanup branch, because they either came too late in the cycle, or they have dependencies on other branches. Important changes are: - The integrator platform is almost multiplatform capable after some reorganization (Linus Walleij) - Minor cleanups on Zynq (Michal Simek) - Lots of changes for Exynos and other Samsung platforms, including further preparations for multiplatform support and the clocks bindings are rearranged" * tag 'tags/cleanup2-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits) devicetree: fix newly added exynos sata bindings ARM: EXYNOS: Fix compilation error in cpuidle.c ARM: S5P64X0: Explicitly include linux/serial_s3c.h in mach/pm-core.h ARM: EXYNOS: Remove hardware.h file ARM: SAMSUNG: Remove hardware.h inclusion ARM: S3C24XX: Remove invalid code from hardware.h dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock ARM: dts: Keep some essential LDOs enabled for arndale-octa board ARM: dts: Disable MDMA1 node for arndale-octa board ARM: S3C64XX: Fix build for implicit serial_s3c.h inclusion serial: s3c: Fix build of header without serial_core.h preinclusion ARM: EXYNOS: Allow wake-up using GIC interrupts ARM: EXYNOS: Stop using legacy Samsung PM code ARM: EXYNOS: Remove PM initcalls and useless indirection ARM: EXYNOS: Fix abuse of CONFIG_PM ARM: SAMSUNG: Move s3c_pm_check_* prototypes to plat/pm-common.h ARM: SAMSUNG: Move common save/restore helpers to separate file ARM: SAMSUNG: Move Samsung PM debug code into separate file ARM: SAMSUNG: Consolidate PM debug functions ARM: SAMSUNG: Use debug_ll_addr() to get UART base address ...
2014-04-05Merge tag 'drivers-3.15' of ↵Linus Torvalds20-147/+3046
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ...
2014-04-05Merge tag 'fixes-non-critical-3.15' of ↵Linus Torvalds3-3/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-critical bug fixes from Arnd Bergmann: "Lots of isolated bug fixes that were not found to be important enough to be submitted before the merge window or backported into stable kernels. The vast majority of these came out of Arnd's randconfig testing and just prevents running into build-time bugs in configurations that we do not care about in practice" * tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits) ARM: at91: fix a typo ARM: moxart: fix CPU selection ARM: tegra: fix board DT pinmux setup ARM: nspire: Fix compiler warning IXP4xx: Fix DMA masks. Revert "ARM: ixp4xx: Make dma_set_coherent_mask common, correct implementation" IXP4xx: Fix Goramo Multilink GPIO conversion. Revert "ARM: ixp4xx: fix gpio rework" ARM: tegra: make debug_ll code build for ARMv6 ARM: sunxi: fix build for THUMB2_KERNEL ARM: exynos: add missing include of linux/module.h ARM: exynos: fix l2x0 saved regs handling ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK ARM: samsung: select ATAGS where necessary ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic ARM: samsung: allow serial driver to be disabled ARM: s5pv210: enable IDE support in MACH_TORBRECK ARM: s5p64x0: fix building with only one soc type ARM: s3c64xx: select power domains only when used ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1 ...
2014-04-02clk: shmobile: fix setting paretn clock rateBen Dooks1-1/+1
If the driver needs to change a clock rate, then it must be propogated through the MSTP clock to the parent clock (such as shdi0 -> sd0). Without this we cannot up-rate default clocks which are really slow (such as the mmcif1 which defaults to 12MHz where it could be running at 97MHz) Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-31clk: shmobile: rcar-gen2: fix lb/sd0/sd1/sdh clock parent to pll1Ben Dooks1-4/+4
The clock generator for rcar-gen2 has the lb, sdh, sd0 and sd1 clocks parented to pll1_div2 where the hardware diagram shows these to be directly fed from pll1. This fixes the initial rate for sdh0 clock to be 97.5MHz instead of the reported 48MHz where the manual says the default register values are for 97.5MHz. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-29Merge tag 'exynos-cleanup' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3 Merge "Exynos cleanup for v3.15" from Kukjin Kim: - reorganize code for - add support reserve memory for mfc-v7 - consolidate exynos4 and exynos5 machine codes - add generic compatible strings for exynos4 and exynos5 - update DT with generic compatible strings - move clk related dt-binding header file in dt-bindings/clock * tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock ARM: dts: Update Exynos DT files with generic compatible strings ARM: EXYNOS: Add generic compatible strings ARM: EXYNOS: Consolidate exynos4 and exynos5 machine files ARM: EXYNOS: Consolidate CPU init code ARM: SAMSUNG: Introduce generic Exynos4 and 5 helpers ARM: EXYNOS: Add support to reserve memory for MFC-v7 ARM: SAMSUNG: Reorganize calls to reserve memory for MFC Conflicts: arch/arm/mach-exynos/exynos.c Signed-off-by; Arnd Bergmann <arnd@arndb.de>
2014-03-29Merge branches 'samsung/cleanup', 'samsung/exynos-clk' and ↵Arnd Bergmann7-90/+346
'samsung/exynos-clk2' into next/cleanup3 These are dependencies for the following Samsung branches Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-29Merge tag 'samsung-pm-1' of ↵Arnd Bergmann7-90/+346
http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers Merge "Samsung S2R PM updates for v3.15" from Kukjin Kim: From Tomasz Figa: This series reworks suspend/resume handling of Samsung clock drivers to cover more SoC specific aspects that are beyond simple register save and restore. The goal is to have all the suspend/resume code that touches the clock controller in single place, which is the clock driver. * tag 'samsung-pm-1' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Drop legacy Exynos4 clock suspend/resume code clk: samsung: exynos4: Add remaining suspend/resume handling clk: samsung: Drop old suspend/resume code clk: samsung: s3c64xx: Move suspend/resume handling to SoC driver clk: samsung: exynos5420: Move suspend/resume handling to SoC driver clk: samsung: exynos5250: Move suspend/resume handling to SoC driver clk: samsung: exynos4: Move suspend/resume handling to SoC driver clk: samsung: Provide common helpers for register save/restore clk: exynos4: Remove remnants of non-DT support Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-27clk: Fix minor errors in of_clk_init() function commentsSylwester Nawrocki1-2/+2
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-27clk: reverse default clk provider initialization order in of_clk_init()Sylwester Nawrocki1-1/+1
This restores the default clocks registration order as parsed from devicetree, i.e. as before commit 1771b10d605d26ccee771a7fb4b08718 "clk: respect the clock dependencies in of_clk_init", for when there is no explicit parent clock dependencies between clock providers specified in the device tree. It prevents regressions (boot failure, division by 0 errors) on imx and exynos platforms. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-26clk: sirf: update copyright years to 2014Barry Song3-3/+6
Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-26clk: mmp: try to use closer one when do round rateChao Xie1-3/+7
The orignal code will use the bigger rate between "previous rate" and "current rate" when caculate the rate. In fact, hardware cares about the closest one. So choose the closer rate between "previous rate" and "current rate". Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-26clk: mmp: fix the wrong calculation formulaChao Xie1-5/+5
The formula is numerator/denominator = Fin / (Fout * factor) So Fout = Fin * denominator / (numerator * factor). Current clk_factor_round_rate and clk_factor_recalc_rate use wrong formula. This patch will fix them. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-26clk: mmp: fix wrong mask when calculate denominatorChao Xie1-1/+1
The code has typo when calculate denominator. It should use den_mask instead of num_mask. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-27Merge tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx into ↵Arnd Bergmann1-27/+62
next/cleanup2 Merge "arm: Xilinx Zynq cleanup patches for v3.15" from Michal Simek: - Redesign SLCR initialization to enable driver developing which targets SLCR space * tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Add waituart implementation ARM: zynq: Move of_clk_init from clock driver ARM: zynq: Introduce zynq_slcr_unlock() ARM: zynq: Add and use zynq_slcr_read/write() helper functions ARM: zynq: Make zynq_slcr_base static ARM: zynq: Map I/O memory on clkc init ARM: zynq: Hang iomapped slcr address on device_node ARM: zynq: Split slcr in two parts ARM: zynq: Move clock_init from slcr to common arm: dt: zynq: Add fclk-enable property to clkc node [Arnd: remove SOC_BUS support from pull request] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-25clk: st: Support for A9 MUX clocksGabriel FERNANDEZ1-0/+19
The patch supports the A9-mux clocks used by ClockGenA9 A9-mux clock : Multiplexer inside ClockGenA9. A9 clock can be driven by either PLL or External clock (with an optional divide-by-2). This is implemented as 3-parent clock : PLL, Ext-clk OR Ext-clk/2 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ1-0/+139
The patch added support for DT registration of ClockGenA9/DDR/GPU ClockgenA9/DDR : It includes c32 type PLL (also in ClockgenA1x), hence only CLK_OF_DECLARE implementation is required. ClockgenGPU : It includes c65 type PLL (also in ClockgenAx), hence only CLK_OF_DECLARE implementation is required. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Support for QUADFS inside ClockGenB/C/D/E/FGabriel FERNANDEZ2-1/+1040
The patch supports the 216/432/660 type Quad Frequency Synthesizers used by ClockGenB/C/D/E/F QUADFS clock : It includes support for all 216/432/660 type Quad Frequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock, with clock rate calculated reading H/w settings done at BOOT. QuadFS have 4 outputs : chan0 chan1 chan2 chan3 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Support for VCC-mux and MUX clocksGabriel FERNANDEZ1-0/+272
The patch supports the VCC-mux and MUX clocks used by ClockGenC/F VCC-mux clock : Divider-Multiplexer-Gate inside ClockGenC/F It includes support for each channel : 4-parent Multiplexer, Post Divide by 1, 2, 4 or 8, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider, clk_mux, clk_gate and clk_composite (to combine all) MUX clock : 2-parent clock used inside ClockGenC/F. The clock is implemented using generic clocks implemented in the kernel clk_mux. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ3-1/+608
The patch supports the c65/c32 type PLLs used by ClockGenA(s) PLL clock : It includes support for all c65/c32 type PLLs inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock, with clock rate calculated reading H/w settings done at BOOT. c65 PLLs have 2 outputs : HS and LS c32 PLLs have 1-4 outputs : ODFx Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-25clk: st: Support for DIVMUX and PreDiv ClocksGabriel FERNANDEZ3-0/+531
The patch supports the DIVMUX and PreDiv clocks used by ClockGenA(s) DIVMUX clock : Divider-Multiplexer-Gate inside ClockGenA(s) It includes support for each channel : 3-parent Multiplexer, Divider for each Parent, Gate to switch OFF the output channel. The clock is implemented using generic clocks implemented in the kernel clk_divider and clk_mux. PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide the oscillator clock by factor-of-16. The clock is implemented using generic clocks implemented in the kernel clk_divider. Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-24clk: support hardware-specific debugfs entriesAlex Elder1-0/+4
Add a new clk_ops->debug_init method to allow a clock hardware driver to populate the clock's debugfs directory with entries beyond those common for every clock. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-24clk: s2mps11: Use of_get_child_by_nameKrzysztof Kozlowski1-1/+1
of_find_node_by_name() walks over all nodes and can thus walk outside of the parent node. Use of_get_child_by_name() instead. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-24clk: s2mps11: Fix possible NULL pointer dereferenceKrzysztof Kozlowski1-1/+1
If parent device does not have of_node set the s2mps11_clk_parse_dt() returned NULL. This NULL was later passed to of_clk_add_provider() which dereferenced it in pr_debug() call. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: <stable@vger.kernel.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: hisilicon: fix warning from smatchZhangfei Gao1-8/+7
drivers/clk/hisilicon/clk-hi3620.c:338 mmc_clk_delay() warn: always true condition '(para >= 0) => (0-u32max >= 0)' Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: shmobile: add CPG driver for rz-platformsWolfram Sang2-0/+104
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20clk: turn rate change failed warning into pr_debugSascha Hauer1-1/+1
If a rate change failed it's the opportunity of the caller to handle this. Do not spam the log with a message. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-21dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clockTushar Behera1-1/+1
Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-03-19clk: respect the clock dependencies in of_clk_initGregory CLEMENT1-4/+79
Until now the clock providers were initialized in the order found in the device tree. This led to have the dependencies between the clocks not respected: children clocks could be initialized before their parent clocks. Instead of forcing each platform to manage its own initialization order, this patch adds this work inside the framework itself. Using the data of the device tree the of_clk_init function now delayed the initialization of a clock provider if its parent provider was not ready yet. The strict dependency check (all parents of a given clk must be initialized) was added by Boris BREZILLON Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: mpc85xx: Update the driver to align to new clock bindingsTang Yuantian1-22/+48
The clock bindings for Freescale CoreNet platform are updated. So, the driver needs to be updated accordingly. The main changes include: - Added a new node to present the input system clock - Changed PLL and MUX's compatible string Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: at91: optimization of the set_rate callbackJean-Jacques Hiblot1-30/+8
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: at91: fix programmable clk irq handlingJean-Jacques Hiblot2-93/+89
The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: at91: propagate rate change on system clksBoris BREZILLON1-1/+1
System clks are just gates, and thus do not provide any rate operations. Authorize clk rate change to be propagated to system clk parents. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: at91: replace prog clk round_rate with determine_rateBoris BREZILLON1-28/+28
Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'clk-hisi' of ↵Mike Turquette6-39/+129
https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
2014-03-19clk: sunxi: fix thinko in commentEmilio López1-1/+1
This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: sunxi: fix some calculationsEmilio López1-3/+3
Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19clk: sunxi: fix A20 PLL4 calculationEmilio López1-0/+7
Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-19Merge tag 'sunxi-clk-for-3.15' of https://bitbucket.org/emiliolopez/linux ↵Mike Turquette1-25/+265
into clk-next-sunxi Allwinner sunXi SoCs clock changes This adds support for the new, more correct clock node naming and gets the A10 compatibles in line with the rest of the other SoCs. It also adds support for the USB, GMAC and A31's PLL6 clocks. Some of these changes also require DT modifications that will be merged via arm-soc.
2014-03-19clk: hisi: remove static variableHaojian Zhuang4-42/+72
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hip04: add clock driverHaojian Zhuang3-1/+59
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hisi: assign missing clk to tableHaojian Zhuang1-0/+2
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-18clk: socfpga: Fix section mismatch warningDinh Nguyen1-1/+1
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-18Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette1-1/+24
clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
2014-03-18clk: clk-s2mps11: Add support for clocks in S5M8767 MFDTushar Behera2-2/+9
Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-18clk: clk-s2mps11: Refactor for including support for other MFD clocksTushar Behera1-4/+16
The clocks in S2MPS11 and S5M8767 are managed in the same way, baring a difference in the register offset. It would be better to update existing S2MPS11 driver to support the clocks in S5M8767, rather than creating an almost duplicate driver altogether. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-18clk: add MOXA ART SoCs clock driverJonas Jensen2-0/+98
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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