linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2017-09-13	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	114	-1037/+8040
2017-09-10	Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Linus Torvalds	4	-210/+21
2017-09-01	clk: si5351: fix PLL reset	Russell King	1	-7/+5
2017-09-01	clk: at91: clk-generated: make gclk determine audio_pll rate	Quentin Schulz	1	-6/+57
2017-09-01	clk: at91: clk-generated: create function to find best_diff	Quentin Schulz	1	-14/+27
2017-09-01	clk: at91: add audio pll clock drivers	Quentin Schulz	2	-0/+537
2017-09-01	clk: at91: clk-generated: remove useless divisor loop	Quentin Schulz	1	-13/+12
2017-09-01	clk: mb86s7x: Drop non-building driver	Andreas Färber	2	-391/+0
2017-08-31	clk: ti: check for null return in strrchr to avoid null dereferencing	Colin Ian King	1	-1/+1
2017-08-31	clk: Don't write error code into divider register	Alex Frid	1	-2/+4
2017-08-31	clk: uniphier: add video input subsystem clock	Katsuhiro Suzuki	1	-0/+6
2017-08-31	clk: uniphier: add audio system clock	Katsuhiro Suzuki	1	-0/+12
2017-08-31	clk: stm32h7: Add stm32h743 clock driver	Gabriel Fernandez	2	-0/+1411
2017-08-31	clk: gate: expose clk_gate_ops::is_enabled	Gabriel Fernandez	1	-1/+2
2017-08-31	clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()	Gabriel Fernandez	1	-6/+6
2017-08-31	clk: uniphier: add PXs3 clock data	Masahiro Yamada	3	-0/+43
2017-08-31	clk: hi6220: change watchdog clock source	Leo Yan	1	-3/+3
2017-08-31	clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808	Elaine Zhang	1	-2/+2
2017-08-31	clk: cs2000: Add cs2000_set_saved_rate	Gaku Inami	1	-4/+10
2017-08-31	clk: imx51: propagate rate across ipu_di*_sel	Lucas Stach	1	-4/+4
2017-08-31	Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kern...	Stephen Boyd	4	-0/+1531
2017-08-30	clk: sunxi: fix uninitialized access	Arnd Bergmann	1	-0/+4
2017-08-30	clk: versatile: make clk_ops const	Bhumika Goyal	1	-1/+1
2017-08-30	ARC: clk: introduce HSDK pll driver	Eugeniy Paltsev	3	-0/+439
2017-08-30	clk: zte: constify clk_div_table	Arvind Yadav	1	-3/+3
2017-08-30	clk: imx: constify clk_div_table	Arvind Yadav	5	-12/+12
2017-08-30	clk: uniphier: add ethernet clock control support	Kunihiko Hayashi	1	-0/+10
2017-08-30	clk: gemini: hands off PCI OE bit	Linus Walleij	1	-7/+0
2017-08-30	clk: ux500: prcc: constify clk_ops.	Arvind Yadav	1	-3/+3
2017-08-30	clk: ux500: sysctrl: constify clk_ops.	Arvind Yadav	1	-4/+4
2017-08-30	clk: ux500: prcmu: constify clk_ops.	Arvind Yadav	1	-7/+7
2017-08-30	clk: sunxi-ng: Provide a default reset hook	Maxime Ripard	1	-0/+12
2017-08-30	clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock	Chen-Yu Tsai	1	-8/+2
2017-08-30	clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switching	Chen-Yu Tsai	2	-0/+110
2017-08-30	clk: sunxi-ng: Add interface to query or configure MMC timing modes.	Chen-Yu Tsai	3	-0/+75
2017-08-24	clk: sunxi-ng: Add sun4i/sun7i CCU driver	Priit Laes	4	-0/+1531
2017-08-23	clk: msm8996-gcc: add missing smmu clks	Srinivas Kandagatla	1	-0/+28
2017-08-23	clk: tegra: Fix Tegra210 PLLU initialization	Alex Frid	1	-2/+4
2017-08-23	clk: tegra: Correct Tegra210 UTMIPLL poweron delay	Alex Frid	1	-3/+3
2017-08-23	clk: tegra: Fix T210 PLLRE registration	Alex Frid	1	-20/+1
2017-08-23	clk: tegra: Update T210 PLLSS (D2/DP) registration	Alex Frid	1	-39/+9
2017-08-23	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	4	-49/+10
2017-08-23	clk: tegra: don't warn for pll_d2 defaults unnecessarily	Peter De Schrijver	1	-2/+4
2017-08-23	clk: tegra: change post IDDQ release delay to 5us	Peter De Schrijver	1	-1/+1
2017-08-23	clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C	Alex Frid	1	-1/+2
2017-08-23	clk: tegra: Fix T210 effective NDIV calculation	Alex Frid	1	-4/+5
2017-08-23	clk: tegra: Init cfg structure in _get_pll_mnp	Peter De Schrijver	1	-0/+2
2017-08-23	clk: tegra210: remove non-existing VFIR clock	Peter De Schrijver	1	-1/+0
2017-08-23	clk: tegra: disable SSC for PLL_D2	Peter De Schrijver	1	-1/+1
2017-08-23	clk: tegra: Enable PLL_SS for Tegra210	Peter De Schrijver	1	-1/+1