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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-08-05clk: qcom: gpucc-sm8150: Add SC8180x supportBjorn Andersson1-0/+12
2021-08-05clk: qcom: smd-rpm: Add mdm9607 clocksKonrad Dybcio1-0/+23
2021-08-05clk: qcom: rpmcc: Add support for MSM8953 RPM clocks.Vladimir Lypak1-0/+37
2021-08-05clk: qcom: smd: Add support for SM6115 rpm clocksIskren Chernev1-0/+42
2021-08-05clk: qcom: smd: Add support for SM6125 rpm clocksMartin Botka1-0/+56
2021-08-05clk: qcom: gdsc: Ensure regulator init state matches GDSC stateBjorn Andersson1-18/+36
2021-08-05clk: imx6q: fix uart earlycon unworkDong Aisheng1-1/+1
2021-08-05clk: stm32mp1: Switch to clk_divider.determine_rateMartin Blumenstingl1-7/+3
2021-08-05clk: stm32h7: Switch to clk_divider.determine_rateMartin Blumenstingl1-4/+4
2021-08-05clk: stm32f4: Switch to clk_divider.determine_rateMartin Blumenstingl1-4/+4
2021-08-05clk: bcm2835: Switch to clk_divider.determine_rateMartin Blumenstingl1-5/+4
2021-08-05clk: divider: Implement and wire up .determine_rate by defaultMartin Blumenstingl1-0/+23
2021-08-05clk: palmas: Add a missing SPDX license headerJason Wang1-9/+1
2021-08-03Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds5-7/+25
2021-07-31clk: fix leak on devm_clk_bulk_get_all() unwindBrian Norris1-1/+8
2021-07-29clk: rockchip: make rk3308 ddrphy4x clock criticalYunhao Tian1-0/+1
2021-07-29clk: rockchip: drop GRF dependency for rk3328/rk3036 pll typesPeter Geis1-1/+1
2021-07-27clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_opsDmitry Osipenko1-0/+10
2021-07-27clk: x86: Rename clk-lpt to more specific clk-lpss-atomAndy Shevchenko2-7/+7
2021-07-27clk: lmk04832: drop redundant fallthrough statementsLiam Beguin1-18/+0
2021-07-27clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167Miles Chen1-15/+10
2021-07-27clk: qcom: dispcc-sm8250: Add additional parent clocks for DPBjorn Andersson1-10/+12
2021-07-27clk: qcom: smd-rpm: Fix MSM8936 RPM_SMD_PCNOC_A_CLKShawn Guo1-1/+1
2021-07-27clk: mediatek: Add MT8192 vencsys clock supportChun-Jie Chen3-0/+60
2021-07-27clk: mediatek: Add MT8192 vdecsys clock supportChun-Jie Chen3-0/+101
2021-07-27clk: mediatek: Add MT8192 scp adsp clock supportChun-Jie Chen3-0/+57
2021-07-27clk: mediatek: Add MT8192 msdc clock supportChun-Jie Chen3-0/+92
2021-07-27clk: mediatek: Add MT8192 mmsys clock supportChun-Jie Chen3-0/+115
2021-07-27clk: mediatek: Add MT8192 mfgcfg clock supportChun-Jie Chen3-0/+57
2021-07-27clk: mediatek: Add MT8192 mdpsys clock supportChun-Jie Chen3-0/+89
2021-07-27clk: mediatek: Add MT8192 ipesys clock supportChun-Jie Chen3-0/+64
2021-07-27clk: mediatek: Add MT8192 imp i2c wrapper clock supportChun-Jie Chen3-0/+126
2021-07-27clk: mediatek: Add MT8192 imgsys clock supportChun-Jie Chen3-0/+77
2021-07-27clk: mediatek: Add MT8192 camsys clock supportChun-Jie Chen3-0/+114
2021-07-27clk: mediatek: Add MT8192 audio clock supportChun-Jie Chen3-0/+125
2021-07-27clk: mediatek: Add MT8192 basic clocks supportChun-Jie Chen5-4/+1358
2021-07-27clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providersChun-Jie Chen2-0/+31
2021-07-27clk: mediatek: Add configurable enable control to mtk_pll_dataChun-Jie Chen2-14/+21
2021-07-27clk: mediatek: Fix asymmetrical PLL enable and disable controlChun-Jie Chen1-4/+16
2021-07-27clk: mediatek: Get regmap without syscon compatible checkChun-Jie Chen4-4/+4
2021-07-26clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen1-1/+1
2021-07-26clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen1-0/+9
2021-07-26clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen1-4/+4
2021-07-26clk: hisilicon: hi3559a: select RESET_HISIRandy Dunlap1-0/+1
2021-07-26clk: stm32f4: fix post divisor setup for I2S/SAI PLLsDario Binacchi1-5/+5
2021-07-26clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2Lad Prabhakar1-1/+2
2021-07-20clk: qcom: Add video clock controller driver for SC7280Taniya Das3-0/+334
2021-07-20clk: qcom: Add graphics clock controller driver for SC7280Taniya Das3-0/+500
2021-07-20clk: qcom: Add display clock controller driver for SC7280Taniya Das3-0/+918
2021-07-19clk: renesas: r9a07g044: Add clock and reset entries for ADCLad Prabhakar1-0/+6