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path: root/drivers/clk/zynqmp/divider.c
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2022-01-24clk: zynqmp: replace warn_once with pr_debug for failed clock opsMichael Tretter1-6/+6
The warning that a clock operation failed is only printed once. However, the function is called for various different clocks. The limit hides the warnings if different clocks are affected by the failures. The clock ops might fail if the firmware that handles the clocks is misconfigured. Therefore, replace the pr_warn_once with pr_debug to allow the user to see all errors if necessary. By default, hide the error messages and let drivers handle the errors. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Link: https://lore.kernel.org/r/20220119115434.2042017-1-m.tretter@pengutronix.de Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Handle divider specific read only flagRajan Vaja1-1/+9
Add support for divider specific read only CCF flag (CLK_DIVIDER_READ_ONLY). Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-5-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific divider clock flagsRajan Vaja1-1/+24
Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-3-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific common clock flagsRajan Vaja1-2/+3
Currently firmware passes CCF specific flags to ZynqMP clock driver. So firmware needs to be updated if CCF flags are changed. The firmware should have its own 'flag number space' that is distinct from the common clk framework's 'flag number space'. So define and use ZynqMP specific common clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-2-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-11clk: zynqmp: divider: Add missing description for 'max_div'Lee Jones1-0/+1
Fixes the following W=1 kernel build warning(s): drivers/clk/zynqmp/divider.c:46: warning: Function parameter or member 'max_div' not described in 'zynqmp_clk_divider' Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Rajan Vaja <rajan.vaja@xilinx.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210126124540.3320214-22-lee.jones@linaro.org Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tero Kristo <kristo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-10Merge tag 'clk-for-linus' of ↵Linus Torvalds1-8/+19
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This time around we have four lines of diff in the core framework, removing a function that isn't used anymore. Otherwise the main new thing for the common clk framework is that it is selectable in the Kconfig language now. Hopefully this will let clk drivers and clk consumers be testable on more than the architectures that support the clk framework. The goal is to introduce some Kunit tests for the framework. Outside of the core framework we have the usual set of various driver updates and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the largest addition this time around in terms of lines of code. After that the x86 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or upcoming SoCs. After that the dirstat shows the usual suspects working on their SoC support by fixing minor bugs, correcting data and converting some of their DT bindings to YAML. Core: - Allow the COMMON_CLK config to be selectable New Drivers: - Clk driver for Baikal-T1 SoCs - Mediatek MT6765 clock support - Support for Intel Agilex clks - Add support for X1830 and X1000 Ingenic SoC clk controllers - Add support for the new Renesas RZ/G1H (R8A7742) SoC - Add support for Qualcomm's MSM8939 Generic Clock Controller Updates: - Support IDT VersaClock 5P49V5925 - Bunch of updates for HSDK clock generation unit (CGU) driver - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver - Enable supply regulators for GPU gdscs on Qualcomm SoCs - Add support for Si5342, Si5344 and Si5345 chips - Support custom flags in Xilinx zynq firmware - Various small fixes to the Xilinx clk driver - A single minor rounding fix for the legacy Allwinner clock support - A few patches from Abel Vesa as preparation of adding audiomix clock support on i.MX - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3 drivers - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on aarch64 hardware - A series from Peng Fan to improve i.MX8M clock drivers, using composite clock for core and bus clk slice - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined bit rates - A couple changes for EMC frequency scaling on Tegra210 - Support for CPU frequency scaling on Tegra20/Tegra30 - New clk gate for CSI test pattern generator on Tegra210 - Regression fixes for Samsung exynos542x and exynos5433 SoCs - Use of fallthrough; attribute for Samsung s3c24xx - Updates and fixup HDMI and video clocks on Meson8b - Fixup reset polarity on Meson8b - Fix GPU glitch free mux switch on Meson gx and g12 - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2 - Two more conversions of Renesas DT bindings to json-schema - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits) clk: mediatek: Remove ifr{0,1}_cfg_regs structures clk: baikal-t1: remove redundant assignment to variable 'divider' clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible" dt-bindings: clock: Add a missing include to MMP Audio Clock binding dt: Add bindings for IDT VersaClock 5P49V5925 clk: vc5: Add support for IDT VersaClock 5P49V6965 clk: Add Baikal-T1 CCU Dividers driver clk: Add Baikal-T1 CCU PLLs driver dt-bindings: clk: Add Baikal-T1 CCU Dividers binding dt-bindings: clk: Add Baikal-T1 CCU PLLs binding clk: mediatek: assign the initial value to clk_init_data of mtk_mux clk: mediatek: Add MT6765 clock support clk: mediatek: add mt6765 clock IDs dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC CLK: HSDK: CGU: add support for 148.5MHz clock CLK: HSDK: CGU: support PLL bypassing CLK: HSDK: CGU: check if PLL is bypassed first clk: clk-si5341: Add support for the Si5345 series ...
2020-05-26clk: zynqmp: Make zynqmp_clk_get_max_divisor staticYueHaibing1-1/+1
Fix sparse warning: drivers/clk/zynqmp/divider.c:259:5: warning: symbol 'zynqmp_clk_get_max_divisor' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20200403083040.37748-1-yuehaibing@huawei.com Reviewed-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26clk: zynqmp: Update fraction clock check from custom type flagsTejas Patel1-2/+4
Older firmware version sets BIT(13) in clkflag to mark a divider as fractional divider. Updated firmware version sets BIT(4) in type flags to mark a divider as fractional divider since BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk framework flags. To support both old and new firmware version, consider BIT(13) from clkflag and BIT(4) from type_flag to check if divider is fractional or not. To maintain compatibility BIT(13) of clkflag in firmware will not be used in future for any purpose and will be marked as unused. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lkml.kernel.org/r/1584048699-24186-3-git-send-email-jolly.shah@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26clk: zynqmp: Fix divider2 calculationTejas Patel1-5/+12
zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock, considering best possible combination of DIV1 and DIV2. To find best possible values of DIV1 and DIV2, DIV1's parent rate should be consider and not DIV2's parent rate since it would rate of div1 clock. Consider a below topology, out_clk->div2_clk->div1_clk->fixed_parent where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk. Existing code divides parent rate of div2_clk's clock instead of div1_clk's parent rate, which is wrong. Fix the same by considering div1's parent clock rate. Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation") Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lkml.kernel.org/r/1583185843-20707-3-git-send-email-jolly.shah@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26clk: zynqmp: Limit bestdiv with maxdivRajan Vaja1-0/+2
Clock divider value should not be greater than maximum divider value. So use minimum of best divider or maximum divider value. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lkml.kernel.org/r/1583185843-20707-2-git-send-email-jolly.shah@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock_getdividerRajan Vaja1-4/+2
Use direct function call instead of using eemi ops for clock_getdivider. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-9-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for clock_setdividerRajan Vaja1-2/+1
Use direct function call instead of using eemi ops for clock_setdivider. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-8-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-04-28firmware: xilinx: Remove eemi ops for query_dataRajan Vaja1-2/+1
Use direct function call for query_data instead of using eemi ops. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Link: https://lore.kernel.org/r/1587761887-4279-4-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-23clk: zynqmp: Add support for clock with CLK_DIVIDER_POWER_OF_TWO flagTejas Patel1-5/+31
Existing clock divider functions is not checking for base of divider. So, if any clock divider is power of 2 then clock rate calculation will be wrong. Add support to calculate divider value for the clocks with CLK_DIVIDER_POWER_OF_TWO flag. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lkml.kernel.org/r/1575527759-26452-7-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-23clk: zynqmp: Fix divider calculationRajan Vaja1-0/+46
zynqmp_clk_divider_round_rate() returns actual divider value after calculating from parent rate and desired rate, even though that rate is not supported by single divider of hardware. It is also possible that such divisor value can be achieved through 2 different dividers. As, Linux tries to set such divisor value(out of range) in single divider set divider is getting failed. Fix the same by computing best possible combination of two divisors which provides more accurate clock rate. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lkml.kernel.org/r/1575527759-26452-6-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-23clk: zynqmp: Add support for get max dividerRajan Vaja1-0/+36
To achieve best possible rate, maximum limit of divider is required while computation. Get maximum supported divisor from firmware. To maintain backward compatibility assign maximum possible value(0xFFFF) if query for max divisor is not successful. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lkml.kernel.org/r/1575527759-26452-5-git-send-email-rajan.vaja@xilinx.com Acked-by: Michal Simek <michal.simek@xilinx.com> [sboyd@kernel.org: Remove else return and just return] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11clk: zynqmp: fix check for fractional clockMichael Tretter1-3/+6
The firmware sets BIT(13) in clkflag to mark a divider as fractional divider. The clock driver copies the clkflag straight to the flags of the common clock framework. In the common clk framework flags, BIT(13) is defined as CLK_DUTY_CYCLE_PARENT. Add a new field to the zynqmp_clk_divider to specify if a divider is a fractional devider. Set this field based on the clkflag when registering a divider. At the same time, unset BIT(13) from clkflag when copying the flags to the common clk framework flags. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11clk: zynqmp: do not export zynqmp_clk_register_* functionsMichael Tretter1-1/+0
The zynqmp_clk_register_* functions are internal functions of the driver. Only clkc.c uses these functions to register these clocks. Therefore, there is no need to export these functions. The gate and pll already don't export their register_* functions. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11drivers: clk: zynqmp: Allow zero divisor valueRajan Vaja1-0/+7
Zero divider is valid and default for some of ZynqMP clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO for the clock is set. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-09drivers: clk: Add ZynqMP clock driverJolly Shah1-0/+217
This patch adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Tejas Patel <tejasp@xilinx.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Acked-by: Olof Johansson <olof@lixom.net> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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