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path: root/drivers/clk/tegra
AgeCommit message (Expand)AuthorFilesLines
2017-01-30PM / OPP: Update OPP users to put referenceViresh Kumar1-11/+6
2016-11-10clk: tegra: dfll: Use builtin_platform_driver to simplify the codeWei Yongjun1-6/+1
2016-11-04clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modularPaul Gortmaker1-14/+2
2016-11-01clk: tegra: dfll: improve function-level documentationJulia Lawall1-5/+5
2016-08-24clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2Vince Hsu1-2/+2
2016-06-30clk: tegra: Initialize UTMI PLL when enabling PLLUAndrew Bresticker6-598/+531
2016-06-23clk: tegra: Micro-optimize Tegra210 clock setupThierry Reding1-4/+4
2016-06-23clk: tegra: Make sor_safe the parent of dpaux and dpaux1Thierry Reding1-2/+2
2016-06-22clk: tegra: Mark timer clock as criticalThierry Reding1-1/+1
2016-06-17clk: tegra: Enable sor1 and sor1_src on Tegra210Thierry Reding1-0/+2
2016-06-17clk: tegra: Squash sor1 safe/brick/src into a single muxThierry Reding2-12/+12
2016-06-17clk: tegra: Disable spread spectrum on pll_d2Thierry Reding1-2/+3
2016-06-10clk: tegra: Fixup post dividers on Tegra210Thierry Reding1-47/+47
2016-05-27remove lots of IS_ERR_VALUE abusesArnd Bergmann1-1/+1
2016-05-20Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds19-114/+369
2016-05-18Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-0/+58
2016-05-09Merge tag 'tegra-for-4.7-phy' of git://git.kernel.org/pub/scm/linux/kernel/gi...Arnd Bergmann1-0/+58
2016-05-02Merge tag 'tegra-for-4.7-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd19-114/+427
2016-04-28clk: tegra: dfll: Reformat CVB frequency tableThierry Reding1-25/+25
2016-04-28clk: tegra: dfll: Properly clean up on failure and removalThierry Reding4-4/+48
2016-04-28clk: tegra: dfll: Make code more comprehensibleThierry Reding3-41/+37
2016-04-28clk: tegra: dfll: Reference CVB table instead of copying dataThierry Reding3-27/+17
2016-04-28clk: tegra: dfll: Update kerneldocThierry Reding1-5/+5
2016-04-28clk: tegra: Fix PLL_U post divider and initial rate on Tegra30Lucas Stach1-5/+6
2016-04-28clk: tegra: Initialize PLL_C to sane rate on Tegra30Lucas Stach1-0/+1
2016-04-28clk: tegra: Fix pllre Tegra210 and add pll_re_out1Rhyland Klein3-2/+66
2016-04-28clk: tegra: Add sor_safe clockThierry Reding2-0/+5
2016-04-28clk: tegra: dpaux and dpaux1 are fixed factor clocksThierry Reding3-2/+12
2016-04-28clk: tegra: Add dpaux1 clockThierry Reding3-0/+3
2016-04-28clk: tegra: Use correct parent for dpaux clockThierry Reding1-1/+1
2016-04-28clk: tegra: Add fixed factor peripheral clock typeThierry Reding3-0/+138
2016-04-28clk: tegra: Special-case mipi-cal parent on Tegra114Thierry Reding2-2/+6
2016-04-28clk: tegra: Remove trailing blank lineThierry Reding1-1/+0
2016-04-28clk: tegra: Constify peripheral clock registersThierry Reding5-7/+7
2016-04-28clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLsAndrew Bresticker1-0/+58
2016-04-28treewide: Fix typos in printkMasanari Iida1-1/+1
2016-03-29clk: tegra: Make reset_control_ops constPhilipp Zabel1-1/+1
2016-03-02clk: tegra: Remove CLK_IS_ROOTStephen Boyd5-14/+8
2016-02-02clk: tegra: super: Fix sparse warnings for functions not declared as staticJon Hunter1-3/+3
2016-02-02clk: tegra: Fix sparse warnings for functions not declared as staticJon Hunter1-17/+19
2016-02-02clk: tegra: Fix sparse warning for pll_mJon Hunter1-1/+1
2016-02-02clk: tegra: Use definition for pll_u override bitJon Hunter1-1/+1
2016-02-02clk: tegra: Fix warning caused by pll_u failing to lockJon Hunter1-2/+0
2016-02-02clk: tegra: Fix clock sources for Tegra210 EMCJon Hunter1-1/+2
2016-02-02clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter3-0/+3
2016-02-02clk: tegra: Add missing of_node_put()Amitoj Kaur Chawla1-2/+4
2016-02-02clk: tegra: Fix PLLE SS coefficientsMark Kuo1-6/+12
2016-02-02clk: tegra: Fix typos around clearing PLLE bits during enableRhyland Klein1-2/+2
2016-02-02clk: tegra: Do not disable PLLE when under hardware controlMark Kuo1-7/+15
2016-02-02clk: tegra: Fix pllx dyn step calculationRhyland Klein1-5/+5