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path: root/drivers/clk/tegra
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2016-01-20Merge tag 'asm-generic-for-linus' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds1-2/+2
2015-12-17clk: tegra: Read correct IDDQ register in PLL_SS registrationBill Huang1-4/+7
2015-12-17clk: tegra: Fix WARN_ON in PLL_RE registrationBill Huang1-1/+2
2015-12-17clk: tegra: pll: Fix issues with rates for VCO PLLsAndrew Bresticker1-4/+12
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein5-0/+2868
2015-12-17clk: tegra: Add Super Gen5 LogicBill Huang2-13/+132
2015-12-17clk: tegra: pll: Add logic for SSBill Huang2-1/+28
2015-12-17clk: tegra: pll: Add dyn_ramp callbackRhyland Klein2-0/+11
2015-12-17clk: tegra: pll: Add Set_default logicBill Huang2-11/+39
2015-12-17clk: tegra: pll: Adjust vco_min if SDM presentBill Huang2-0/+32
2015-12-17clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein2-5/+52
2015-12-17clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein2-2/+346
2015-11-20clk: tegra: pll: Update PLLM handlingDanny Huang3-51/+10
2015-11-20clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rateRhyland Klein5-304/+379
2015-11-20clk: tegra: pll: Add code to handle if resets are supported by PLLBill Huang2-0/+16
2015-11-20clk: tegra: pll: Add logic for out-of-table rates for T210Rhyland Klein2-2/+35
2015-11-20clk: tegra: pll: Add logic for handling SDM dataRhyland Klein2-2/+79
2015-11-20clk: tegra: pll: Don't unconditionally set LOCK flagsRhyland Klein5-45/+55
2015-11-20clk: tegra: pll: Change misc_reg count from 3 to 6Bill Huang1-1/+3
2015-11-20clk: tegra: pll: Update warning messageRhyland Klein1-1/+2
2015-11-20clk: tegra: pll: Simplify clk_enable_pathRhyland Klein1-54/+22
2015-11-20clk: tegra: pll: Add tegra_pll_wait_for_lock to clk headerRhyland Klein2-0/+6
2015-11-20clk: tegra: periph: Add new periph clks and muxes for Tegra210Rhyland Klein2-5/+434
2015-11-20clk: tegra: Constify pdiv-to-hw mappingsThierry Reding6-15/+15
2015-11-18clk: tegra: Format tables consistentlyThierry Reding4-652/+646
2015-11-18clk: tegra: Miscellaneous coding style cleanupsThierry Reding5-25/+19
2015-11-18clk: tegra: Fix 26 MHz oscillator frequencyThierry Reding3-3/+3
2015-11-16tegra/clk-divider: fix wrong do_div() usageNicolas Pitre1-2/+2
2015-10-20Merge tag 'tegra-for-4.4-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Michael Turquette7-113/+163
2015-10-20clk: tegra: Modify tegra_audio_clk_init to accept more pllsRhyland Klein5-11/+56
2015-10-20clk: tegra: Update struct tegra_clk_pll_params kerneldocThierry Reding1-3/+15
2015-10-20clk: tegra: Fix comments for structure definitionsRhyland Klein1-37/+37
2015-10-20clk: tegra: dfll: Monitor code is DEBUG_FS onlyThierry Reding1-50/+49
2015-10-12clk: tegra: delete unneeded of_node_putJulia Lawall1-3/+1
2015-09-16clk: tegra: dfll: Properly protect OPP listThierry Reding1-1/+7
2015-09-15clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen2-14/+8
2015-08-25clk: tegra: Fix some static checker problemsStephen Boyd2-7/+9
2015-08-25Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/gi...Stephen Boyd10-9/+2304
2015-08-24clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd1-4/+4
2015-08-24clk: tegra: Convert to clk_hw based provider APIsStephen Boyd2-10/+10
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd16-16/+2
2015-07-27clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-13/+15
2015-07-20clk: tegra: Properly include clk.hStephen Boyd16-16/+2
2015-07-16clk: tegra: Add the DFLL as a possible parent of the cclk_g clockTuomas Tynkkynen1-1/+3
2015-07-16clk: tegra: Save/restore CCLKG_BURST_POLICY on suspendTuomas Tynkkynen1-0/+14
2015-07-16clk: tegra: Add Tegra124 DFLL clocksource platform driverTuomas Tynkkynen4-4/+172
2015-07-16clk: tegra: Add DFLL DVCO reset control for Tegra124Paul Walmsley1-0/+68
2015-07-16clk: tegra: Introduce ability for SoC-specific reset control callbacksMikko Perttunen2-8/+34
2015-07-16clk: tegra: Add functions for parsing CVB tablesTuomas Tynkkynen2-0/+207
2015-07-16clk: tegra: Add closed loop support for the DFLLTuomas Tynkkynen1-3/+663