| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-03-24 | clk: tegra: Use NULL for pointer initialization | Stephen Boyd | 1 | -1/+1 |
| 2020-03-12 | clk: tegra: Remove audio clocks configuration from clock driver | Sowjanya Komatineni | 5 | -15/+10 |
| 2020-03-12 | clk: tegra: Remove tegra_pmc_clk_init along with clk ids | Sowjanya Komatineni | 9 | -201/+19 |
| 2020-03-12 | clk: tegra: Remove CLK_M_DIV fixed clocks | Sowjanya Komatineni | 6 | -45/+0 |
| 2020-03-12 | clk: tegra: Fix Tegra PMC clock out parents | Sowjanya Komatineni | 1 | -6/+6 |
| 2020-03-12 | clk: tegra: Add Tegra OSC to clock lookup | Sowjanya Komatineni | 6 | -0/+14 |
| 2020-03-12 | clk: tegra: Add support for OSC_DIV fixed clocks | Sowjanya Komatineni | 6 | -0/+34 |
| 2020-01-31 | Merge branches 'clk-imx', 'clk-ti', 'clk-xilinx', 'clk-nvidia', 'clk-qcom', '... | Stephen Boyd | 5 | -11/+15 |
| 2020-01-10 | clk: tegra20/30: Explicitly set parent clock for Video Decoder | Dmitry Osipenko | 2 | -2/+2 |
| 2020-01-10 | clk: tegra20/30: Don't pre-initialize displays parent clock | Dmitry Osipenko | 2 | -4/+0 |
| 2020-01-10 | clk: tegra: divider: Check UART's divider enable-bit state on rate's recalcul... | Dmitry Osipenko | 1 | -2/+7 |
| 2020-01-10 | clk: tegra: clk-dfll: Remove call to pm_runtime_irq_safe() | Sowjanya Komatineni | 1 | -2/+1 |
| 2020-01-08 | clk: tegra: Mark fuse clock as critical | Stephen Warren | 1 | -1/+5 |
| 2019-12-24 | clk: tegra: Fix double-free in tegra_clk_init() | Dmitry Osipenko | 1 | -1/+3 |
| 2019-11-13 | clk: tegra: Use match_string() helper to simplify the code | YueHaibing | 1 | -8/+4 |
| 2019-11-11 | clk: tegra: Fix build error without CONFIG_PM_SLEEP | YueHaibing | 1 | -0/+2 |
| 2019-11-11 | clk: tegra: Optimize PLLX restore on Tegra20/30 | Dmitry Osipenko | 2 | -18/+32 |
| 2019-11-11 | clk: tegra: Add suspend and resume support on Tegra210 | Sowjanya Komatineni | 3 | -4/+163 |
| 2019-11-11 | clk: tegra: Share clk and rst register defines with Tegra clock driver | Sowjanya Komatineni | 2 | -45/+45 |
| 2019-11-11 | clk: tegra: Use fence_udelay() during PLLU init | Sowjanya Komatineni | 1 | -4/+4 |
| 2019-11-11 | clk: tegra: clk-dfll: Add suspend and resume support | Sowjanya Komatineni | 3 | -0/+59 |
| 2019-11-11 | clk: tegra: clk-super: Add restore-context support | Sowjanya Komatineni | 1 | -0/+27 |
| 2019-11-11 | clk: tegra: clk-super: Fix to enable PLLP branches to CPU | Sowjanya Komatineni | 4 | -1/+39 |
| 2019-11-11 | clk: tegra: periph: Add restore_context support | Sowjanya Komatineni | 2 | -0/+37 |
| 2019-11-11 | clk: tegra: Support for OSC context save and restore | Sowjanya Komatineni | 2 | -0/+16 |
| 2019-11-11 | clk: tegra: pll: Save and restore pll context | Sowjanya Komatineni | 1 | -32/+54 |
| 2019-11-11 | clk: tegra: pllout: Save and restore pllout context | Sowjanya Komatineni | 1 | -0/+9 |
| 2019-11-11 | clk: tegra: divider: Save and restore divider rate | Sowjanya Komatineni | 1 | -0/+11 |
| 2019-11-11 | clk: tegra: Reimplement SOR clocks on Tegra210 | Thierry Reding | 1 | -16/+55 |
| 2019-11-11 | clk: tegra: Reimplement SOR clock on Tegra124 | Thierry Reding | 1 | -9/+13 |
| 2019-11-11 | clk: tegra: Rename sor0_lvds to sor0_out | Thierry Reding | 3 | -8/+8 |
| 2019-11-11 | clk: tegra: Move SOR0 implementation to Tegra124 | Thierry Reding | 2 | -8/+49 |
| 2019-11-11 | clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC | Thierry Reding | 2 | -2/+2 |
| 2019-11-11 | clk: tegra: Add Tegra20/30 EMC clock implementation | Dmitry Osipenko | 5 | -52/+339 |
| 2019-07-17 | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 1 | -8/+12 |
| 2019-06-28 | Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/... | Linus Torvalds | 1 | -0/+2 |
| 2019-06-25 | clk: tegra: Do not enable PLL_RE_VCO on Tegra210 | Thierry Reding | 1 | -1/+0 |
| 2019-06-25 | clk: tegra: Warn if an enabled PLL is in IDDQ | Thierry Reding | 1 | -1/+5 |
| 2019-06-25 | clk: tegra: Do not warn unnecessarily | Thierry Reding | 1 | -2/+3 |
| 2019-06-25 | clk: tegra210: fix PLLU and PLLU_OUT1 | JC Kuo | 1 | -4/+4 |
| 2019-06-19 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 | Thomas Gleixner | 1 | -4/+1 |
| 2019-06-14 | clk: tegra210: Fix default rates for HDA clocks | Jon Hunter | 1 | -0/+2 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282 | Thomas Gleixner | 1 | -9/+1 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 | Thomas Gleixner | 20 | -240/+20 |
| 2019-05-30 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 | Thomas Gleixner | 5 | -49/+5 |
| 2019-05-21 | treewide: Add SPDX license identifier - Makefile/Kconfig | Thomas Gleixner | 1 | -0/+1 |
| 2019-05-15 | clk: Remove io.h from clk-provider.h | Stephen Boyd | 4 | -0/+4 |
| 2019-05-07 | Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and... | Stephen Boyd | 4 | -40/+77 |
| 2019-05-07 | Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-... | Stephen Boyd | 1 | -1/+1 |
| 2019-04-25 | clk: tegra: divider: Mark Memory Controller clock as read-only | Dmitry Osipenko | 1 | -1/+2 |
