linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2017-08-23	clk: tegra: Fix Tegra210 PLLU initialization	Alex Frid	1	-2/+4
2017-08-23	clk: tegra: Correct Tegra210 UTMIPLL poweron delay	Alex Frid	1	-3/+3
2017-08-23	clk: tegra: Fix T210 PLLRE registration	Alex Frid	1	-20/+1
2017-08-23	clk: tegra: Update T210 PLLSS (D2/DP) registration	Alex Frid	1	-39/+9
2017-08-23	clk: tegra: Re-factor T210 PLLX registration	Alex Frid	4	-49/+10
2017-08-23	clk: tegra: don't warn for pll_d2 defaults unnecessarily	Peter De Schrijver	1	-2/+4
2017-08-23	clk: tegra: change post IDDQ release delay to 5us	Peter De Schrijver	1	-1/+1
2017-08-23	clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C	Alex Frid	1	-1/+2
2017-08-23	clk: tegra: Fix T210 effective NDIV calculation	Alex Frid	1	-4/+5
2017-08-23	clk: tegra: Init cfg structure in _get_pll_mnp	Peter De Schrijver	1	-0/+2
2017-08-23	clk: tegra210: remove non-existing VFIR clock	Peter De Schrijver	1	-1/+0
2017-08-23	clk: tegra: disable SSC for PLL_D2	Peter De Schrijver	1	-1/+1
2017-08-23	clk: tegra: Enable PLL_SS for Tegra210	Peter De Schrijver	1	-1/+1
2017-08-23	clk: tegra: fix SS control on PLL enable/disable	Peter De Schrijver	1	-20/+24
2017-07-21	clk: Convert to using %pOF instead of full_name	Rob Herring	1	-7/+5
2017-04-04	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter	1	-4/+4
2017-04-04	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver	3	-0/+19
2017-04-04	clk: tegra: Propagate clk_out_x rate to parent	Alex Frid	1	-2/+4
2017-03-20	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding	2	-2/+2
2017-03-20	clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on	Peter De Schrijver	1	-0/+2
2017-03-20	clk: tegra: Add SATA seq input control	Peter De Schrijver	1	-0/+25
2017-03-20	clk: tegra: Add Tegra210 special resets	Peter De Schrijver	1	-0/+85
2017-03-20	clk: tegra: Rework pll_u	Peter De Schrijver	2	-197/+272
2017-03-20	clk: tegra: Implement reset control reset	Mikko Perttunen	1	-0/+16
2017-03-20	clk: tegra: Fix disable unused for clocks sharing enable bit	Peter De Schrijver	1	-0/+3
2017-03-20	clk: tegra: Handle UTMIPLL IDDQ	Peter De Schrijver	1	-0/+26
2017-03-20	clk: tegra: Add aclk	Peter De Schrijver	1	-0/+10
2017-03-20	clk: tegra: Add super clock mux/divider	Peter De Schrijver	2	-5/+89
2017-03-20	clk: tegra: Define Tegra210 DMIC clocks	Peter De Schrijver	3	-1/+28
2017-03-20	clk: tegra: Fix constness for peripheral clocks	Peter De Schrijver	2	-4/+4
2017-03-20	clk: tegra: Define Tegra210 DMIC sync clocks	Peter De Schrijver	3	-24/+73
2017-03-20	clk: tegra: Add CEC clock	Peter De Schrijver	6	-0/+6
2017-03-20	clk: tegra: Fix type for m field	Peter De Schrijver	1	-1/+1
2017-03-20	clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation	Peter De Schrijver	1	-1/+7
2017-03-20	clk: tegra: Don't warn for PLL defaults unnecessarily	Peter De Schrijver	1	-6/+12
2017-03-20	clk: tegra: Remove non-existing pll_m_out1 clock	Peter De Schrijver	1	-5/+0
2017-03-20	clk: tegra: Correct afi clock parent	Peter De Schrijver	1	-1/+1
2017-03-20	clk: tegra: Fix ISP clock modelling	Peter De Schrijver	3	-2/+11
2017-03-20	clk: tegra: Fix pll_a1 iddq register, add pll_a1	Peter De Schrijver	1	-1/+2
2017-02-25	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	3	-0/+625
2017-02-03	clk: tegra: Add BPMP clock driver	Thierry Reding	3	-0/+625
2017-01-30	PM / OPP: Update OPP users to put reference	Viresh Kumar	1	-11/+6
2016-11-10	clk: tegra: dfll: Use builtin_platform_driver to simplify the code	Wei Yongjun	1	-6/+1
2016-11-04	clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modular	Paul Gortmaker	1	-14/+2
2016-11-01	clk: tegra: dfll: improve function-level documentation	Julia Lawall	1	-5/+5
2016-08-24	clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2	Vince Hsu	1	-2/+2
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker	6	-598/+531
2016-06-23	clk: tegra: Micro-optimize Tegra210 clock setup	Thierry Reding	1	-4/+4
2016-06-23	clk: tegra: Make sor_safe the parent of dpaux and dpaux1	Thierry Reding	1	-2/+2
2016-06-22	clk: tegra: Mark timer clock as critical	Thierry Reding	1	-1/+1