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path: root/drivers/clk/tegra/cvb.c
AgeCommit message (Expand)AuthorFilesLines
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-10/+1
2019-02-06clk: tegra: dfll: CVB calculation alignment with the regulatorJoseph Lo1-5/+7
2016-11-01clk: tegra: dfll: improve function-level documentationJulia Lawall1-5/+5
2016-04-28clk: tegra: dfll: Properly clean up on failure and removalThierry Reding1-0/+16
2016-04-28clk: tegra: dfll: Make code more comprehensibleThierry Reding1-28/+27
2015-09-15clk: tegra: Unlock top rates for Tegra124 DFLL clockMikko Perttunen1-7/+0
2015-07-16clk: tegra: Add functions for parsing CVB tablesTuomas Tynkkynen1-0/+140