index
:
linux
WIP-syscall
master
mmu_gather-race-fix
n900-dt
n900-dt-with-ssi
n900-dts-twl5030
n900-modem-rework
n900-omapdrm
next
proc-cmdline
sc18is600
ssi
ssi-cleaned
ssi-cleaned-dt
ssi-cleaned-dt2
ssi-cleaned-dt3
tty-splice
twl4030-madc-cleanup
Linux Kernel (branches are rebased on master from time to time)
Linus Torvalds
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
drivers
/
clk
/
tegra
/
clk-tegra210.c
Age
Commit message (
Expand
)
Author
Files
Lines
2019-11-11
clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC
Thierry Reding
1
-1
/
+1
2019-07-17
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-8
/
+12
2019-06-28
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...
Linus Torvalds
1
-0
/
+2
2019-06-25
clk: tegra: Do not enable PLL_RE_VCO on Tegra210
Thierry Reding
1
-1
/
+0
2019-06-25
clk: tegra: Warn if an enabled PLL is in IDDQ
Thierry Reding
1
-1
/
+5
2019-06-25
clk: tegra: Do not warn unnecessarily
Thierry Reding
1
-2
/
+3
2019-06-25
clk: tegra210: fix PLLU and PLLU_OUT1
JC Kuo
1
-4
/
+4
2019-06-14
clk: tegra210: Fix default rates for HDA clocks
Jon Hunter
1
-0
/
+2
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
Thomas Gleixner
1
-12
/
+1
2019-04-23
clk: core: replace clk_{readl,writel} with {readl,writel}
Jonas Gorski
1
-3
/
+3
2018-12-14
clk: tegra: Fix maximum audio sync clock for Tegra124/210
Jon Hunter
1
-1
/
+8
2018-10-16
clk: tegra210: Include size.h for compilation ease
Stephen Boyd
1
-0
/
+1
2018-10-16
clk: tegra: Fixes for MBIST work around
Joseph Lo
1
-3
/
+3
2018-07-25
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
Peter De-Schrijver
1
-2
/
+12
2018-05-18
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
Dmitry Osipenko
1
-1
/
+1
2018-03-12
clk: tegra: Mark HCLK, SCLK and EMC as critical
Dmitry Osipenko
1
-2
/
+1
2018-03-08
clk: tegra: MBIST work around for Tegra210
Peter De Schrijver
1
-2
/
+342
2018-03-08
clk: tegra: Add la clock for Tegra210
Peter De Schrijver
1
-0
/
+14
2017-11-01
clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()
Nicolin Chen
1
-2
/
+2
2017-10-19
clk: tegra: Fix sor1_out clock implementation
Thierry Reding
1
-0
/
+47
2017-08-23
clk: tegra: Fix Tegra210 PLLU initialization
Alex Frid
1
-2
/
+4
2017-08-23
clk: tegra: Correct Tegra210 UTMIPLL poweron delay
Alex Frid
1
-3
/
+3
2017-08-23
clk: tegra: Re-factor T210 PLLX registration
Alex Frid
1
-1
/
+1
2017-08-23
clk: tegra: don't warn for pll_d2 defaults unnecessarily
Peter De Schrijver
1
-2
/
+4
2017-08-23
clk: tegra: Fix T210 effective NDIV calculation
Alex Frid
1
-4
/
+5
2017-08-23
clk: tegra210: remove non-existing VFIR clock
Peter De Schrijver
1
-1
/
+0
2017-08-23
clk: tegra: disable SSC for PLL_D2
Peter De Schrijver
1
-1
/
+1
2017-04-04
clk: tegra: Don't reset PLL-CX if it is already enabled
Jon Hunter
1
-4
/
+4
2017-04-04
clk: tegra: Add missing Tegra210 clocks
Peter De Schrijver
1
-0
/
+7
2017-03-20
clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on
Peter De Schrijver
1
-0
/
+2
2017-03-20
clk: tegra: Add SATA seq input control
Peter De Schrijver
1
-0
/
+25
2017-03-20
clk: tegra: Add Tegra210 special resets
Peter De Schrijver
1
-0
/
+85
2017-03-20
clk: tegra: Rework pll_u
Peter De Schrijver
1
-23
/
+272
2017-03-20
clk: tegra: Handle UTMIPLL IDDQ
Peter De Schrijver
1
-0
/
+26
2017-03-20
clk: tegra: Add aclk
Peter De Schrijver
1
-0
/
+10
2017-03-20
clk: tegra: Define Tegra210 DMIC clocks
Peter De Schrijver
1
-0
/
+3
2017-03-20
clk: tegra: Define Tegra210 DMIC sync clocks
Peter De Schrijver
1
-0
/
+6
2017-03-20
clk: tegra: Add CEC clock
Peter De Schrijver
1
-0
/
+1
2017-03-20
clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation
Peter De Schrijver
1
-1
/
+7
2017-03-20
clk: tegra: Don't warn for PLL defaults unnecessarily
Peter De Schrijver
1
-6
/
+12
2017-03-20
clk: tegra: Remove non-existing pll_m_out1 clock
Peter De Schrijver
1
-5
/
+0
2017-03-20
clk: tegra: Fix ISP clock modelling
Peter De Schrijver
1
-0
/
+1
2017-03-20
clk: tegra: Fix pll_a1 iddq register, add pll_a1
Peter De Schrijver
1
-1
/
+2
2016-06-30
clk: tegra: Initialize UTMI PLL when enabling PLLU
Andrew Bresticker
1
-179
/
+3
2016-06-23
clk: tegra: Micro-optimize Tegra210 clock setup
Thierry Reding
1
-4
/
+4
2016-06-23
clk: tegra: Make sor_safe the parent of dpaux and dpaux1
Thierry Reding
1
-2
/
+2
2016-06-17
clk: tegra: Enable sor1 and sor1_src on Tegra210
Thierry Reding
1
-0
/
+2
2016-06-17
clk: tegra: Disable spread spectrum on pll_d2
Thierry Reding
1
-2
/
+3
2016-06-10
clk: tegra: Fixup post dividers on Tegra210
Thierry Reding
1
-47
/
+47
2016-05-27
remove lots of IS_ERR_VALUE abuses
Arnd Bergmann
1
-1
/
+1
[next]