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path: root/drivers/clk/sunxi/clk-sunxi.c
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2015-10-17ARM: sunxi: Add R8 supportMaxime Ripard1-0/+1
2015-08-31Merge tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds1-204/+23
2015-08-24clk: sunxi: Convert to clk_hw based provider APIsStephen Boyd1-5/+5
2015-08-24clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd1-1/+1
2015-08-24clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()Stephen Boyd1-1/+1
2015-08-12clk: sunxi: Add a simple gates driverMaxime Ripard1-177/+0
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-0/+2
2015-07-28clk: sunxi: make use of of_clk_parent_fill helper functionDinh Nguyen1-10/+4
2015-07-27clk: fix some determine_rate implementationsBoris Brezillon1-2/+4
2015-07-27clk: change clk_ops' ->determine_rate() prototypeBoris Brezillon1-11/+9
2015-07-20clk: sunxi: Include clk.h and remove unused clkdev.h includesStephen Boyd1-0/+2
2015-07-09Merge tag 'sunxi-late-for-4.2' of https://git.kernel.org/pub/scm/linux/kernel...Kevin Hilman1-0/+1
2015-07-05ARM: sunxi: Add Machine support for A33Vishnu Patekar1-0/+1
2015-05-05clk: sunxi: Fix of_io_request_and_map error checkMaxime Ripard1-0/+2
2015-03-25clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6Chen-Yu Tsai1-1/+2
2015-03-25clk: sunxi: Make divs clocks specify which output is the base factor clockChen-Yu Tsai1-12/+25
2015-03-21clk: sunxi: Register divs clocks before factor clocksChen-Yu Tsai1-3/+3
2015-03-21clk: sunxi: Add "cpu" to list of protected clocks for sun5iChen-Yu Tsai1-0/+1
2015-03-21clk: sunxi: Add muxable ahb factors clock for sun5i and sun7iChen-Yu Tsai1-0/+52
2015-02-23clk: sunxi: Move USB clocks to separate fileChen-Yu Tsai1-88/+0
2015-02-21Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/...Linus Torvalds1-40/+222
2015-02-02clk: Add rate constraints to clocksTomeu Vizoso1-0/+2
2015-01-25sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede1-0/+1
2015-01-14clk: sunxi: Remove custom phase functionMaxime Ripard1-37/+0
2015-01-06clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai1-1/+1
2015-01-05ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxiHans de Goede1-0/+1
2014-12-21clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede1-1/+10
2014-12-21clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai1-0/+208
2014-12-21clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai1-1/+0
2014-11-23clk: sunxi: Implement A31 PLL6 as a divs clock for 2x outputChen-Yu Tsai1-12/+16
2014-11-23clk: sunxi: Specify number of child clocks for divs clocksChen-Yu Tsai1-2/+9
2014-11-23clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driverChen-Yu Tsai1-7/+0
2014-11-11clk: sunxi: unify APB1 clockEmilio López1-5/+2
2014-10-21clk: sunxi: Add support for bus clock gates on Allwinner A80 SoCChen-Yu Tsai1-0/+31
2014-10-21clk: sunxi: make factors clock mux mask configurableChen-Yu Tsai1-0/+1
2014-09-27clk: sunxi: Move mbus to mod0 fileMaxime Ripard1-57/+0
2014-09-27clk: sunxi: Move mod0 clock to a file of its ownMaxime Ripard1-1/+0
2014-09-27clk: sunxi: Introduce mbus compatibleMaxime Ripard1-0/+1
2014-09-27clk: sunxi: factors: Invert the probing logicMaxime Ripard1-92/+3
2014-09-13clk: sunxi: add correct divider table for sun4i-apb0 clockChen-Yu Tsai1-0/+9
2014-07-28clk: sunxi: add __iomem markings to MMIO pointersEmilio López1-5/+5
2014-07-04clk: sunxi: Add A23 clocks supportChen-Yu Tsai1-0/+101
2014-07-04clk: sunxi: Add support for table-based divider clocksChen-Yu Tsai1-4/+5
2014-07-04clk: sunxi: move "ahb_sdram" to protected clock listChen-Yu Tsai1-5/+3
2014-07-04clk: sunxi: register clock gates with clkdevChen-Yu Tsai1-0/+1
2014-06-11clk: sun6i: Protect SDRAM gating bitMaxime Ripard1-0/+1
2014-06-11clk: sun6i: Protect CPU clockMaxime Ripard1-0/+1
2014-06-11clk: sunxi: Rework clock protection codeMaxime Ripard1-28/+44
2014-06-11clk: sunxi: Move the GMAC clock to a file of its ownMaxime Ripard1-98/+0
2014-06-11clk: sunxi: Move the 24M oscillator to a file of its ownMaxime Ripard1-57/+0