linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2017-05-10	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	17	-53/+710
2017-04-28	clk: sunxi-ng: always select CCU_GATE	Arnd Bergmann	1	-1/+1
2017-04-21	Merge tag 'sunxi-clk-for-4.12-2' of https://git.kernel.org/pub/scm/linux/kern...	Stephen Boyd	7	-18/+17
2017-04-19	Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel...	Stephen Boyd	13	-37/+695
2017-04-13	clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code	Chen-Yu Tsai	1	-2/+1
2017-04-13	clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch	Chen-Yu Tsai	2	-3/+3
2017-04-13	clk: sunxi-ng: use 1 as fallback for minimum multiplier	Chen-Yu Tsai	4	-11/+11
2017-04-13	clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change	Chen-Yu Tsai	1	-0/+11
2017-04-13	clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks	Chen-Yu Tsai	2	-0/+61
2017-04-13	clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driver	Tobias Regnery	1	-0/+1
2017-04-13	clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER	Tobias Regnery	1	-0/+1
2017-04-10	clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value	Icenowy Zheng	1	-1/+1
2017-04-10	clk: sunxi-ng: fix PRCM CCU ir clk parent	Icenowy Zheng	1	-1/+1
2017-04-06	clk: sunxi-ng: Display index when clock registration fails	Priit Laes	1	-2/+2
2017-04-05	clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor	Chen-Yu Tsai	1	-7/+11
2017-04-05	clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks	Chen-Yu Tsai	1	-18/+52
2017-04-05	clk: sunxi-ng: mult: Support PLL lock detection	Chen-Yu Tsai	2	-0/+4
2017-04-04	clk: sunxi-ng: add support for PRCM CCUs	Icenowy Zheng	4	-0/+247
2017-03-20	clk: sunxi-ng: fix recalc_rate formula of NKMP clocks	Icenowy Zheng	1	-1/+1
2017-03-20	clk: sunxi-ng: Fix div/mult settings for osc12M on A64	Philipp Tomsich	1	-1/+1
2017-03-06	clk: sunxi-ng: sun5i: Fix mux width for csi clock	Priit Laes	1	-1/+1
2017-03-06	clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs	Peter Robinson	1	-0/+8
2017-03-06	clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver	Icenowy Zheng	3	-9/+323
2017-03-06	clk: sunxi-ng: gate: Support common pre-dividers	Chen-Yu Tsai	1	-0/+47
2017-03-06	clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock	Chen-Yu Tsai	1	-1/+1
2017-03-06	clk: sunxi: ccu-sun5i needs nkmp	Arnd Bergmann	1	-0/+1
2017-03-06	clk: sunxi-ng: mp: Adjust parent rate for pre-dividers	Chen-Yu Tsai	1	-0/+8
2017-02-06	clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()	Wei Yongjun	1	-1/+1
2017-02-06	clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i	Arnd Bergmann	1	-0/+1
2017-02-06	clk: sunxi-ng: Check kzalloc() for errors and cleanup error path	Stephen Boyd	1	-0/+15
2017-01-30	clk: sunxi-ng: Add A80 Display Engine CCU	Chen-Yu Tsai	3	-0/+317
2017-01-30	clk: sunxi-ng: Add A80 USB CCU	Chen-Yu Tsai	3	-0/+170
2017-01-30	clk: sunxi-ng: Add A80 CCU	Chen-Yu Tsai	4	-0/+1291
2017-01-30	clk: sunxi-ng: Support separately grouped PLL lock status register	Chen-Yu Tsai	2	-2/+9
2017-01-30	clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT	Chen-Yu Tsai	1	-1/+12
2017-01-30	clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag	Chen-Yu Tsai	1	-0/+15
2017-01-30	clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers	Chen-Yu Tsai	1	-3/+4
2017-01-27	clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for the GPU	Maxime Ripard	1	-1/+1
2017-01-27	clk: sunxi-ng: Call divider_round_rate if we only have a single parent	Maxime Ripard	1	-0/+12
2017-01-23	clk: sunxi-ng: Add sun5i CCU driver	Maxime Ripard	4	-0/+1100
2017-01-23	clk: sunxi-ng: Implement global pre-divider	Maxime Ripard	2	-1/+9
2017-01-23	clk: sunxi-ng: Implement multiplier maximum	Maxime Ripard	6	-20/+32
2017-01-23	clk: sunxi-ng: mult: Fix minimum in round rate	Maxime Ripard	1	-1/+1
2017-01-23	clk: sunxi-ng: Implement factors offsets	Maxime Ripard	8	-29/+79
2017-01-23	clk: sunxi-ng: multiplier: Add fractional support	Maxime Ripard	2	-0/+10
2017-01-20	clk: sunxi-ng: add support for V3s CCU	Icenowy Zheng	4	-0/+666
2017-01-17	clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig	Mylène Josserand	1	-1/+1
2017-01-02	clk: sunxi-ng: A31: Fix spdif clock register	Marcus Cooper	1	-2/+2
2017-01-02	clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33	Icenowy Zheng	1	-1/+1
2017-01-02	clk: sunxi-ng: fix PLL_CPUX adjusting on A33	Icenowy Zheng	1	-0/+10