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path: root/drivers/clk/st
AgeCommit message (Expand)AuthorFilesLines
2015-10-08drivers: clk: st: Correct the pll-type for A9 for stih418Gabriel Fernandez1-0/+194
2015-10-08drivers: clk: st: PLL rate change implementation for DVFSGabriel Fernandez3-10/+216
2015-10-08drivers: clk: st: Support for enable/disable in Clockgen PLLsGabriel Fernandez1-1/+59
2015-10-01clk: st: fix handling result of of_property_count_stringsAndrzej Hajda1-3/+4
2015-09-17drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_xGabriel Fernandez2-10/+10
2015-08-24clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)Stephen Boyd4-16/+16
2015-08-24clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd1-1/+1
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd4-0/+4
2015-07-28clk: st: make use of of_clk_parent_fill helper functionDinh Nguyen2-9/+4
2015-07-20clk: st: Include clk.hStephen Boyd4-0/+4
2015-07-13clk: st: Fix error paths and allocation styleStephen Boyd1-38/+45
2015-07-07drivers: clk: st: Incorrect register offset used for lock_statusPankaj Dev1-1/+1
2015-07-06drivers: clk: st: Fix mux bit-setting for Cortex A9 clocksGabriel Fernandez1-1/+1
2015-07-06drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocksPankaj Dev4-6/+8
2015-07-06drivers: clk: st: Fix flexgen lock initGiuseppe Cavallaro1-0/+2
2015-07-06drivers: clk: st: Fix FSYN channel valuesGabriel Fernandez1-2/+2
2015-07-06drivers: clk: st: Remove unused codeGabriel Fernandez1-4/+0
2015-06-04clk: st: Use of_clk_get_parent_count() instead of open codingGeert Uytterhoeven2-2/+2
2015-05-14clk: st: Silence sparse warningsStephen Boyd4-17/+17
2015-04-01clk: constify of_device_id arrayFabian Frederick3-7/+7
2015-02-18clk: Replace explicit clk assignment with __clk_hw_set_clkJavier Martinez Canillas2-17/+17
2015-01-20clk: st: STiH410: Fix pdiv and fdiv divisor when setting ratePeter Griffin1-4/+15
2014-07-28clk: st: Use round to closest divider flagGabriel FERNANDEZ1-1/+2
2014-07-28clk: st: Update frequency tables for fs660c32 and fs432c65Gabriel FERNANDEZ1-8/+59
2014-07-28clk: st: STiH407: Support for clockgenA9Gabriel FERNANDEZ1-0/+16
2014-07-28clk: st: STiH407: Support for clockgenD0/D2/D3Gabriel FERNANDEZ1-0/+46
2014-07-28clk: st: STiH407: Support for clockgenC0Gabriel FERNANDEZ2-0/+83
2014-07-28clk: st: Add quadfs reset handlingGabriel FERNANDEZ1-0/+5
2014-07-28clk: st: Add polarity bit indicationGabriel FERNANDEZ1-5/+7
2014-07-28clk: st: STiH407: Support for clockgenA0Gabriel FERNANDEZ1-0/+16
2014-07-28clk: st: STiH407: Support for A9 MUX ClocksGabriel FERNANDEZ1-0/+9
2014-07-28clk: st: STiH407: Support for Flexgen ClocksGabriel FERNANDEZ2-1/+332
2014-07-28clk: st: Remove uncessary (void *) castGabriel FERNANDEZ1-4/+4
2014-07-28clk: st: use static const for clkgen_pll_data tablesGabriel FERNANDEZ1-16/+14
2014-07-28clk: st: use static const for stm_fs tablesGabriel FERNANDEZ1-17/+17
2014-05-28clk: st: Terminate of match tableStephen Boyd1-0/+1
2014-05-23clk: st: Fix memory leakValentin Ilie1-1/+3
2014-03-25clk: st: Support for A9 MUX clocksGabriel FERNANDEZ1-0/+19
2014-03-25clk: st: Support for ClockGenA9/DDR/GPUGabriel FERNANDEZ1-0/+139
2014-03-25clk: st: Support for QUADFS inside ClockGenB/C/D/E/FGabriel FERNANDEZ2-1/+1040
2014-03-25clk: st: Support for VCC-mux and MUX clocksGabriel FERNANDEZ1-0/+272
2014-03-25clk: st: Support for PLLs inside ClockGenA(s)Gabriel FERNANDEZ3-1/+608
2014-03-25clk: st: Support for DIVMUX and PreDiv ClocksGabriel FERNANDEZ2-0/+530
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