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2012-12-14Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-0/+1
Pull ARM SoC device-tree updates, take 2, from Olof Johansson: "This branch contains device-tree updates for the SPEAr platform. They had dependencies on earlier branches from this merge window, which is why they were broken out in a separate branch." * tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/ ARM: SPEAr320: DT: Add SPEAr 320 HMI board support ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT ARM: SPEAr1310: Fix AUXDATA for compact flash controller ARM: SPEAr13xx: Remove fields not required for ssp controller ARM: SPEAr1310: Move 1310 specific misc register into machine specific files ARM: SPEAr: DT: Update device nodes ARM: SPEAr: DT: add uart state to fix warning ARM: SPEAr: DT: Modify DT bindings for STMMAC ARM: SPEAr: DT: Fix existing DT support ARM: SPEAr: DT: Update partition info for MTD devices ARM: SPEAr: DT: Update pinctrl list ARM: SPEAr13xx: DT: Add spics gpio controller nodes
2012-11-26ARM: SPEAr1310: Move 1310 specific misc register into machine specific filesVipul Kumar Samar1-0/+1
This patch moves some global macro definitions to the files where they are used. Its a step towards removing spear.h completely later on. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2012-11-21CLK: SPEAr: Remove unused dummy apb_pclkVipul Kumar Samar4-12/+0
Dummy clocks were added for ARM platforms, so that clk_get() for interface clk doesn't fail for amba devices from amba_probe(). Because there is no amba device for SPEAr that doesn't have a valid clock with dev_id for SPEAr, we don't need these dummy clocks. Hence, remove them. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-21CLK: SPEAr: Correct index scanning done for clock synthsDeepak Sikri1-0/+3
The patch corrects the case when the rate table is being scanned for a given frequency, and the search frequency is beyond the maximum frequency indexed in the table. By default, the system should be set at max frequency present in the rate table. This patch correctly returns the corresponding index value. Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-21CLK: SPEAr: Update clock rate tableDeepak Sikri4-21/+89
This patch updates the existing rate tables with new frequencies. Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-21CLK: SPEAr: Add missing clocksVipul Kumar Samar3-0/+16
This patch adds missing clocks: twd and macb. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-21CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocksVipul Kumar Samar5-114/+133
Flag CLK_SET_RATE_PARENT is required for a clock, where we want to propagate clk_set_rate to its parent. This patch adds this to multiple clocks. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com> Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-21CLK: SPEAr13xx: fix parent names of multiple clocksShiraz Hashim2-4/+4
This patch fixes parent names of multiple clocks. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-21CLK: SPEAr13xx: Fix mux clock namesShiraz Hashim2-12/+12
This patch updates mux clock names of multiple clocks. It updates _clk with _mclk to make it more readable. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-21CLK: SPEAr: Fix dev_id & con_id for multiple clocksRajeev Kumar4-41/+49
dev_id & con_id names of multiple clocks are incorrect. This patch fixes these names with the names that come via DT. Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-11-15clk: spear: Add stub functions for spear3[0|1|2]0_clk_init()Axel Lin1-0/+6
This fixes compile error if one of SPEAr3xx implementations is not selected. CC drivers/clk/spear/spear3xx_clock.o drivers/clk/spear/spear3xx_clock.c: In function 'spear3xx_clk_init': drivers/clk/spear/spear3xx_clock.c:599:3: error: implicit declaration of function 'spear300_clk_init' [-Werror=implicit-function-declaration] drivers/clk/spear/spear3xx_clock.c:601:3: error: implicit declaration of function 'spear310_clk_init' [-Werror=implicit-function-declaration] drivers/clk/spear/spear3xx_clock.c:603:3: error: implicit declaration of function 'spear320_clk_init' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors make[3]: *** [drivers/clk/spear/spear3xx_clock.o] Error 1 make[2]: *** [drivers/clk/spear] Error 2 make[1]: *** [drivers/clk] Error 2 make: *** [drivers] Error 2 Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-10-29clk: SPEAr: Vco-pll: Fix compilation warningViresh Kumar1-1/+1
Currently we are getting following warning for SPEAr clk-vco-pll. "warning: i is used uninitialized in this function." This is because we are getting value of i by passing its pointer to another routine. The variables here are really not used uninitialized. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-07-18Clk: SPEAr1340: Update sys clock parent arrayVipul Kumar Samar1-2/+2
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl register bit no. 23:25, with following possibilities 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Out of several possibilities (h/w wise) to select same clock parent for sys_clk, current clock implementation was considering just one value. When bootloader programmed different (valid) value to select a clock parent then Linux breaks. Here, we try to include all possibilities which can lead to same clock selection thus making Linux independent of bootloader selection values. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2012-07-18clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.Vipul Kumar Samar1-2/+2
This patch is to fix typing mistake of clk enable register of i2c1 and uart1. Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2012-07-18Clk:spear6xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-62/+60
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk ras_gen1_synth_gate_clk -> ras_syn1_gclk pll3_48m -> pll3_ Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18Clk:spear3xx:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-94/+86
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk ras_gen1_synth_gate_clk -> ras_syn1_gclk ras_pll3_48m -> ras_pll3_ pll3_48m -> pll3_ Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18clk:spear1310:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-157/+155
The max limit of con_id is 16 and dev_id is 20. As of now for spear1310, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk gmac_phy -> phy_ gmii_125m_pad -> gmii_pad Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-07-18clk:spear1340:Fix: Rename clk ids within predefined limitVipul Kumar Samar1-138/+135
The max limit of con_id is 16 and dev_id is 20. As of now for spear1340, many clk ids are exceeding this predefined limit. This patch rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk gmac_phy -> phy_ gmii_125m_pad_ -> gmii_pad Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-06-25clk: SPEAr600: Fix ethernet clock name for DT based probingStefan Roese1-1/+1
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-20Viresh has movedViresh Kumar10-10/+10
viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-05-14SPEAr13xx: Add common clock framework supportViresh Kumar3-0/+2072
This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based on earlier support for SPEAr3xx family. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@ti.com>
2012-05-12SPEAr: Switch to common clock frameworkViresh Kumar3-0/+957
SPEAr SoCs used its own clock framework since now. From now on they will move to use common clock framework. This patch updates existing SPEAr machine support to adapt for common clock framework. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-05-12SPEAr: clk: Add General Purpose Timer Synthesizer clockViresh Kumar3-1/+172
All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from following equations: Fout= Fin/((2 ^ (N+1)) * (M+1)) This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12SPEAr: clk: Add Fractional Synthesizer clockViresh Kumar3-1/+182
All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from following equations: Fout = Fin / (2 * div) (division factor) div is 17 bits:- 0-13 (fractional part) 14-16 (integer part) div is (16-14 bits).(13-0 bits) (in binary) Fout = Fin/(2 * div) Fout = ((Fin / 10000)/(2 * div)) * 10000 Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000 Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000 div << 14 is simply 17 bit value written at register. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12SPEAr: clk: Add Auxiliary Synthesizer clockViresh Kumar3-1/+242
All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on values of eq, x and y. Fout from synthesizer can be given from two equations: Fout1 = (Fin * X/Y)/2 EQ1 Fout2 = Fin * X/Y EQ2 This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12SPEAr: clk: Add VCO-PLL Synthesizer clockViresh Kumar4-0/+462
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations - In normal mode vco = (2 * M[15:8] * Fin)/N - In Dithered mode vco = (2 * M[15:0] * Fin)/(256 * N) pll_rate = vco/2^p vco and pll are very closely bound to each other, "vco needs to program: mode, m & n" and "pll needs to program p", both share common enable/disable logic and registers. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Reviewed-by: Mike Turquette <mturquette@linaro.org>
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