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2016-02-22clk: socfpga: allow for multiple parents on Arria10 periph clocksDinh Nguyen2-9/+4
There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill() helper function. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-08clk: socfpga: fix __init annotationArnd Bergmann1-1/+1
clang found a bug with the __socfpga_pll_init definition: drivers/clk/socfpga/clk-pll-a10.c:77:15: error: '__section__' attribute only applies to functions and global variables This moves the __init annotation to the right place so the function actually gets discarded. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: socfpga: Add a second parent option for the dbg_base_clkDinh Nguyen2-4/+15
The debug base clock can be bypassed from the main PLL to the OSC1 clock. The bypass register is the staysoc1(0x10) register that is in the clock manager. This patch adds the option to get the correct parent for the debug base clock. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: socfpga: switch to GENMASK()Andy Shevchenko5-5/+4
Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: socfpga: Remove clk.h and clkdev.h includesStephen Boyd7-7/+6
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Remove the include here because this is a provider driver. The clkdev.h include isn't used either, remove it and add in slab.h to make sure things keep compiling. Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-09clk: socfpga: remove a stray tabDan Carpenter1-1/+1
This line was indented too far. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-06-05clk: socfpga: make use of of_clk_parent_fill helper functionDinh Nguyen2-11/+2
Use of_clk_parent_fill to fill in the parent clock's array. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-21clk: socfpga: add a clock driver for the Arria 10 platformDinh Nguyen6-1/+469
The clocks on the Arria 10 platform is a bit different than the Cyclone/Arria 5 platform that it should just have it's own driver. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-21clk: socfpga: update clk.h so for Arria10 platform to useDinh Nguyen2-5/+5
There are 5 possible parent clocks for the SoCFPGA Arria10. Move the define SYSMGR_SDMMC_CTRL_SET and streq() to clk.h so that the Arria clock driver can use. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14clk: socfpga: Silence sparse warningStephen Boyd1-1/+1
drivers/clk/socfpga/clk-periph.c:79:39: warning: Using plain integer as NULL pointer Cc: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-14clk: socfpga: Silence sparse warningStephen Boyd1-1/+1
drivers/clk/socfpga/clk-gate.c:227:40: warning: Using plain integer as NULL pointer Cc: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-05-12Merge tag 'socfpga-clk-update-for-v3.16' of ↵Mike Turquette3-4/+23
git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga Adds support getting the divider registers for the MAIN PLL that was once thought to be hidden.
2014-05-12clk: socfpga: add divider registers to the main pll outputsDinh Nguyen3-4/+23
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-04-30clk: socfpga: fix clock driver for 3.15Dinh Nguyen2-20/+10
commit [1771b10d6 clk: respect the clock dependencies in of_clk_init] exposed a flaw in the socfpga clock driver and prevents the platform from booting on 3.15-rc1. Because the "altr,clk-mgr" is not really a clock, it should not be using CLK_OF_DECLARE, instead we should be mapping the clk-mgr's base address one of the functional clock init function. Use the socfpga_pll_init function to map the clk_mgr_base_addr as this clock should always be initialized first. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Tested-by: Pavel Machek <pavel@denx.de>
2014-03-18clk: socfpga: Fix section mismatch warningDinh Nguyen1-1/+1
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: socfpga: Support multiple parents for the pll clocksDinh Nguyen1-4/+22
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-26clk: socfpga: Fix integer overflow in clock calculationDinh Nguyen1-3/+5
Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by: Graham Moore <grmoore@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-02-18clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk"Dinh Nguyen1-0/+68
The clk-phase property is used to represent the 2 clock phase values that is needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will use the syscon driver to set sdmmc_clk's phase shift that is located in the system manager. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> --- v9: none v8: Use degrees in the clk-phase binding property v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a prepare function to the gate clk that will toggle clock phase setting. Remove the "altr,socfpga-sdmmc-sdr-clk" clock type. v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to set the phase shift settings. v5: Use the "snps,dw-mshc" binding v4: Use the sdmmc_clk prepare function to set the phase shift settings v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is loaded after the clock driver. v2: Use the syscon driver
2014-02-18clk: socfpga: split clk codeSteffen Trumtrar6-306/+462
Move the different kinds of clocks into their own files. The reason is to aid readability of the code. This also goes along with the other SoC-specific clock drivers. The split introduces new structs for the three types of clocks and uses them. Other changes are not done to the code. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: fix define typoSteffen Trumtrar1-3/+3
It should be SOCFPGA instead of SOCFGPA. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: remove unused fieldSteffen Trumtrar1-1/+0
The clk_name field from the socfpga_clk struct is unused. Remove it. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: Remove socfpga_init_clocksDinh Nguyen1-10/+0
The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk. Now that twd-timer's clock phandle is populated in the DTS, we can remove this function. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-02-18clk: socfpga: Look for the GPIO_DB_CLK by its offsetDinh Nguyen1-2/+3
After the patch: "clk: socfpga: Map the clk manager base address in the clock driver" The clk->name field in socfpga_clk_recalc_rate() was getting cleared. Replace looking for the GPIO_DB_CLK by its divider offset instead. Also rename the define SOCFPGA_DB_CLK_OFFSET -> SOCFPGA_GPIO_DB_CLK_OFFSET, as this represents the GPIO_DB_CLK. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
2014-02-18clk: socfpga: Map the clk manager base address in the clock driverDinh Nguyen1-4/+16
The clk manager's base address was being mapped in SOCFPGA's arch code and being extern'ed out to the clock driver. This method is not correct, and the arch code was not really doing anything with that clk manager anyways. This patch moves the mapping of the clk manager's base address in the clock driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all the clocks. Suggested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Arnd Bergmann <arnd@arndb.de> --- v2: Use a static declaration for the clk_mgr_base_addr. Clean up the CLK_OF_DECLARE() as suggested by Arnd.
2013-12-19clk: socfpga: Use NULL instead of 0Sachin Kamat1-1/+1
'div_reg' is a pointer. Assign NULL instead of 0. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-11-27clk: socfpga: Remove check for "reg" property in socfpga_clk_initDinh Nguyen1-3/+1
The function socfpga_clk_init() can support clocks that do not have a divider register, but a fixed-divider that can be read from DTS. Therefore, the "reg" property is not a failing condition for socfpga_clk_init(). Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-10-07clk: socfpga: Fix incorrect sdmmc clock nameDinh Nguyen1-1/+1
The SD/MMC clock is named "sdmmc_clk", and NOT "mmc_clk". Because of this, the SD driver was getting the incorrect clock value. This prevented the SD driver from initializing correctly. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11ARM: socfpga: Add support to gate peripheral clocksDinh Nguyen1-9/+185
Add support to gate the clocks that directly feed peripherals. For clocks with multiple parents, add the ability to determine the correct parent, and also set parents. Also add support to calculate and set the clocks' rate. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Mike Turquette <mturquette@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> CC: Arnd Bergmann <arnd@arndb.de> CC: Olof Johansson <olof@lixom.net> Cc: Pavel Machek <pavel@denx.de> CC: <linux@arm.linux.org.uk> v4: - Add Acked-by: Mike Turquette v3: - Addressed comments from Pavel v2: - Fix space/indent errors - Add streq for strcmp == 0 Signed-off-by: Olof Johansson <olof@lixom.net>
2013-04-14ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entriesDinh Nguyen1-21/+142
With this patch, the socfpga clk driver is able to query the clock and clock rates appropriately. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-07-19ARM: socfpga: initial support for Altera's SOCFPGA platformDinh Nguyen2-0/+52
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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