Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2014-05-12 | clk: socfpga: add divider registers to the main pll outputs | Dinh Nguyen | 1 | -1/+0 |
2014-02-18 | clk: socfpga: Add a clk-phase property to the "altr,socfpga-gate-clk" | Dinh Nguyen | 1 | -0/+68 |
2014-02-18 | clk: socfpga: split clk code | Steffen Trumtrar | 1 | -0/+195 |