linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Collapse)	Author	Files	Lines
2014-05-23	clk: shmobile: Add R8A7740-specific clock support	Ulrich Hecht	1	-0/+1
	Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-05-12	clk: shmobile: r8a7779: Add clocks support	Simon Horman	1	-0/+1
	The R8A7779 SoC has several clocks that are too custom to be supported in a generic driver. Those clocks are all fixed rate clocks with multiplier and divisor set according to boot mode configuration. Based on work for R-Car Gen2 SoCs by Laurent Pinchart. Cc: devicetree@vger.kernel.org Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-03-20	clk: shmobile: add CPG driver for rz-platforms	Wolfram Sang	1	-0/+1
	Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-14	clk: emev2: Add support for emev2 SMU clocks with DT	Takashi Yoshii	1	-1/+1
	Device tree clock binding document for EMMA Mobile EV2 SMU, And Common clock framework based implementation of it. Following nodes are defined to describe clock tree. - renesas,emev2-smu - renesas,emev2-smu-clkdiv - renesas,emev2-smu-gclk These bindings are designed manually based on 19UH0037EJ1000_SMU : System Management Unit User's Manual So far, reparent is not implemented, and is fixed to index #0. Clock tree description is not included, and should be provided by device-tree. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-12-12	clk: shmobile: Add MSTP clock support	Laurent Pinchart	1	-0/+1
	MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-12	clk: shmobile: Add DIV6 clock support	Laurent Pinchart	1	-0/+1
	DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-12	clk: shmobile: Add R-Car Gen2 clocks support	Laurent Pinchart	1	-0/+5
	The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are too custom to be supported in a generic driver. Those clocks can be divided in two categories: - Fixed rate clocks with multiplier and divisor set according to boot mode configuration - Custom divider clocks with SoC-specific divider values This driver supports both. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>