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2016-03-29clk: rockchip: Make reset_control_ops constPhilipp Zabel1-1/+1
The rockchip_softrst_ops structure is never modified. Make it const. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-23Merge tag 'clk-for-linus' of ↵Linus Torvalds11-212/+238
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The clk changes for this release cycle are mostly dominated by new device support in terms of LoC, but there has been some cleanup in the core as well as the usual minor clk additions to various drivers. Core: - parent tracking has been simplified - CLK_IS_ROOT is now a no-op flag, cleaning up drivers has started - of_clk_init() doesn't consider disabled DT nodes anymore - clk_unregister() had an error path bug squashed - of_clk_get_parent_count() has been fixed to only return unsigned ints - HAVE_MACH_CLKDEV is removed now that the last arch user (ARM) is gone New Drivers: - NXP LPC18xx creg - QCOM IPQ4019 GCC - TI dm814x ADPLL - i.MX6QP Updates: - Cyngus audio clks found on Broadcom iProc devices - Non-critical fixes for BCM2385 PLLs - Samsung exynos5433 updates for clk id errors, HDMI support, suspend/resume simplifications - USB, CAN, LVDS, and FCP clks on shmobile devices - sunxi got support for more clks on new SoCs and went through a minor refactoring/rewrite to use a simpler factor clk construct - rockchip added some more clk ids and added suport for fraction dividers - QCOM GDSCs in msm8996 - A new devm helper to make adding custom actions simpler (acked by Greg)" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (197 commits) clk: bcm2835: fix check of error code returned by devm_ioremap_resource() clk: renesas: div6: use RENESAS for #define clk: renesas: Rename header file renesas.h clk: max77{686,802}: Remove CLK_IS_ROOT clk: versatile: Remove CLK_IS_ROOT clk: sunxi: Remove use of variable length array clk: fixed-rate: Remove CLK_IS_ROOT clk: qcom: Remove CLK_IS_ROOT doc: dt: add documentation for lpc1850-creg-clk driver clk: add lpc18xx creg clk driver clk: lpc32xx: fix compilation warning clk: xgene: Add missing parenthesis when clearing divider value clk: mb86s7x: Remove CLK_IS_ROOT clk: x86: Remove clkdev.h and clk.h includes clk: x86: Remove CLK_IS_ROOT clk: mvebu: Remove CLK_IS_ROOT clk: renesas: move drivers to renesas directory clk: si5{14,351,70}: Remove CLK_IS_ROOT clk: scpi: Remove CLK_IS_ROOT clk: s2mps11: Remove CLK_IS_ROOT ...
2016-03-20Merge tag 'armsoc-arm64' of ↵Linus Torvalds1-1/+3
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC 64-bit changes from Arnd Bergmann: "Here's our branch of ARM64 contents for this merge window, now containing all ARM64 changes other than device tree files. - Various new platforms get added: * Allwinner A64 SoC * Annapurna Labs Alpine SoCs * Broadcom Vulcan * Marvell Armada 3700 SoCs * Amlogic S905 - Various defconfig changes to enable platform specific drivers This branch includes the clk git tree to resolve a build-time dependency" * tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) arm64: defconfig: Increase MMC_BLOCK_MINORS to 16 arm64: defconfig: Add Qualcomm sdhci and restart functionality ARM64: Enable Amlogic Meson GXBaby platform arm64: defconfig: Enable Samsung MFD and related configs arm64: alpine: select the Alpine MSI controller driver arm64: defconfig: enable the Alpine family arm64: add Alpine SoC family arm64: defconfig: Enable exynos thermal config arm64: add defconfig options for Allwinner SoCs arm64: defconfig: Enable DesignWare APB GPIO controller arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS clk: samsung: Don't build ARMv8 clock drivers on ARMv7 MAINTAINERS: Add entry for Broadcom Vulcan SoC arm64: cputype info for Broadcom Vulcan arm64: Broadcom Vulcan support arm64: defconfig: Add Broadcom Vulcan to defconfig arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support Documentation: arm: add Marvell Armada 7K and 8K families Documentation: arm: add link to Armada 38x Functional Spec ...
2016-03-16clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036Heiko Stuebner1-1/+1
The emac needs constant and very specific rate but the possible PLL-sources are very limited, so we expect the PLL source to be set manually on per board and don't want it to get changed in an automatic way later. So add the necessary clock-id and disable reparenting on set_rate calls. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-16clk: rockchip: associate the rk3036 HCLK_EMAC clock-idXing Zheng1-1/+1
Associate the new clock id the clock. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Xing Zheng <zhengxing@rock-chips.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-04Merge tag 'v4.6-rockchip-clk2' of ↵Stephen Boyd6-61/+83
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull second batch of rockchip clk updates from Heiko Stuebner: Inclusion of the rk3368 fractional dividers into our handling scheme, fixes for missing error-handling in mmc-phase, inverters and cpu-clocks and some more clock-ids. * tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: include downstream muxes into fractional dividers on rk3368 clk: rockchip: set the clock ids for RK3228 HDMI clk: rockchip: set the clock ids for RK3228 VOP clk: rockchip: add the tsadc clocks found on rk3228 SoCs clk: rockchip: add the new clock ids for RK3228 HDMI clk: rockchip: add the new clock ids for RK3228 VOP clk: rockchip: add id of the tsadc clock found on rk3228 SoCs clk: rockchip: fix coding style for clk-cpu.c clk: rockchip: don't return NULL when registering mmc branch fails clk: rockchip: don't return NULL when registering inverter fails clk: rockchip: check grf when waiting pll lock clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
2016-02-26clk: rockchip: include downstream muxes into fractional dividers on rk3368Elaine Zhang1-37/+60
During the initial conversion to the newly introduced combined fractional dividers+muxes the rk3368 clocks were left out, so convert them now. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26clk: rockchip: set the clock ids for RK3228 HDMIYakir Yang1-4/+4
Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26clk: rockchip: set the clock ids for RK3228 VOPYakir Yang1-3/+3
Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-26clk: rockchip: add the tsadc clocks found on rk3228 SoCsCaesar Wang1-2/+2
This patch adds the needed clocks for rk3228 tsadc. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15clk: rockchip: fix coding style for clk-cpu.cShawn Lin1-1/+1
Fix the issue reported by checkpatch: ERROR: space prohibited before that ',' (ctx:WxW) + writel(clksel->val , cpuclk->reg_base + clksel->reg); Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15clk: rockchip: don't return NULL when registering mmc branch failsShawn Lin1-6/+2
Avoid return NULL if rockchip_clk_register_mmc fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15clk: rockchip: don't return NULL when registering inverter failsShawn Lin1-6/+2
Avoid return NULL if rockchip_clk_register_inverter fails, otherwise rockchip_clk_register_branches print "unknown clock type". The acutal case is that it's a known clock type but we fail to regiser it, which may makes user confuse the reason of failure. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15clk: rockchip: check grf when waiting pll lockShawn Lin1-0/+5
rockchip_clk_get_grf pass on return value from syscon_regmap_lookup_by_phandle, so we check grf to make sure whether to do the following things or not. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15clk: rockchip: disable alt_parent clk in err cases when registering cpuclkShawn Lin1-2/+4
Add clk_disable_unprepare to handle cpuclk->alt_parent if rockchip_clk_register_cpuclk fails. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-15Merge tag 'v4.6-rockchip-clk1' of ↵Michael Turquette7-153/+157
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Introduction of a factor type and a variant containing a gate to be able to also declare factor clocks in their correct place in the clock tree instead of having to register factor clocks in the init callback separately. And as always some more clock-ids and non-regression fixes for mistakes introduced in past kernel releases.
2016-02-04clk: rockchip: convert manually created factor clocks to the new typeHeiko Stuebner5-98/+24
Clean up the init code and move the creation of factor clocks to the appropriate positions coming from the clock architecture diagrams. This also unifies the artificial separation of the hclk_vcodec etc clocks again. We do keep the separate definition of some watchdog and usb480m pseudo clocks for now, as they're not real factor clocks from the clock-tree but placeholders for fixes to come (usb480m gets supplied by the missing driver for the new usbphy type and the watchdog-gate is sitting somewhere else together which we cannot model currently). Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04clk: rockchip: add a factor clock typeHeiko Stuebner2-0/+83
Add a clock type for fixed factor clocks. This allows us to define fixed factor clocks where they appear in the clock hierarchy instead of in the init function. The additional factor_gate type, finally allows us to model some last parts of the clock tree correctly. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-04clk: rockchip: fix parent of hclk_vcodec on rk3036Heiko Stuebner1-1/+1
hclk_vcodec is a child of aclk_vcodec with the fixed factor clock hclk_vcodec_pre in between and not a child of hclk_disp_pre. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-02clk: rockchip: free memory in error cases when registering clock branchesShawn Lin1-2/+7
Add free memeory if rockchip_clk_register_branch fails. Fixes: a245fecbb806 ("clk: rockchip: add basic infrastructure...") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-29Merge branch 'clk-fixes' into clk-nextStephen Boyd2-26/+26
* clk-fixes: clk: rockchip: rk3368: fix some clock gates clk: rockchip: rk3036: rename emac ext source clock clk: rockchip: rk3036: fix the div offset for emac clock clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: fix the FLAGs for clock mux
2016-01-29clk-divider: make sure read-only dividers do not write to their registerHeiko Stuebner1-1/+3
Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: rockchip: Allow sclk_i2s0 and i2s0_frac to change their parents rate on ↵Alexander Kochetkov1-2/+2
rk3188 Allow sclk_i2s0 and i2s0_frac to change their parents rate as that the upstream dividers are purely there to feed sclk_i2s0 Tested on radxarock-lite. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-28clk: rockchip: fix wrong mmc phase shift for rk3228Shawn Lin1-3/+3
mmc sample shift is 0 for rk3228 refer to user manaul. So it's broken if we enable mmc tuning for rk3228. Fixes: 307a2e9ac ("clk: rockchip: add clock controller for rk3228") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26clk: rockchip: add hclk_cpubus to the list of rk3188 critical clocksAlexander Kochetkov1-0/+1
hclk_cpubus needs to keep running because it is needed for devices like the rom, i2s0 or spdif to be accessible via cpu. Without that all accesses to devices (readl/writel) return wrong data. So add it to the list of critical clocks. Fixes: 78eaf6095cc763c ("clk: rockchip: disable unused clocks") Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Cc: stable@vger.kernel.org # 4.1.x- Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-26clk: rockchip: add tsadc clock on rk3066Paweł Jarosz1-1/+1
Set clock id for sclk_tsadc gating clock of tsadc in rk3066 Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25clk: rockchip: fix usbphy-related clocksHeiko Stuebner2-19/+8
The otgphy clocks really only drive the phy blocks. These in turn contain plls that then generate the 480m clocks the clock controller uses to supply some other clocks like uart0, gpu or the video-codec. So fix this structure to actually respect that hirarchy and removed that usb480m fixed-rate clock working as a placeholder till now, as this wouldn't even work if the supplying phy gets turned off while its pll-output gets used elsewhere. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Michael Turquette <mturquette@baylibre.com>
2016-01-25clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for i2s_2chzhangqing1-1/+1
I2S_2CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8chzhangqing1-1/+1
SPDIF_8CH set freq need to select parent and calculate parent freq. so just mark it as the CLK_SET_RATE_PARENT flag. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-25clk: rockchip: rk3368: fix edp_24m parentzhangqing1-1/+1
The edp_24m parent select bit define is: 1'b0:xin24m 1'b1:1'b0(dummy) so adapt the parent sel bit to the currect one. Signed-off-by: zhangqing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-24clk: rockchip: rk3368: fix hdmi_cec gate-registerHeiko Stuebner1-1/+1
Fix a typo making the sclk_hdmi_cec access a wrong register to handle its gate. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
2016-01-24clk: rockchip: rk3368: fix parents of video encoder/decoderHeiko Stuebner1-2/+2
The vdpu and vepu clocks can also be parented to the npll and current parent list also is wrong as it would use the npll as "usbphy" source, so adapt the parent to the correct one. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
2016-01-24clk: rockchip: rk3368: fix cpuclk core dividersHeiko Stuebner1-20/+20
Similar to commit 9880d4277f6a ("clk: rockchip: fix rk3288 cpuclk core dividers") it seems the cpuclk dividers are one to high on the rk3368 as well. And again similar to the previous fix, we opt to make the divider list contain the values to be written to use the same paradigm for them on all supported socs. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
2016-01-24clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-clusterHeiko Stuebner1-1/+1
Both clusters have their mux bit in bit 7 of their respective register. For whatever reason the big cluster currently lists bit 15 which is definitly wrong. Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: zhangqing <zhangqing@rock-chips.com> Cc: stable@vger.kernel.org
2016-01-24clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for hclk_vio_busYakir Yang1-1/+1
HCLK_VIO_BUS is the noc bus controller clock for display module, due to it shouldn't belong to any driver, but we need it enabled, so just mark it as the CLK_IGNORE_UNUSED flag. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3368: fix some clock gatesJianqun xu1-13/+13
Reference to the Rockchip RK3368 TRM v1.1, some clock gates need to be updated. Signed-off-by: Jianqun xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: rename emac ext source clockXing Zheng1-1/+1
There is only support rmii in the RK3036, so we should use the correct ext clock name as described in the TRM. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [update dt-binding document as well] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: fix the div offset for emac clockXing Zheng1-2/+2
Due to reference to old version TRM, there are incorrect emac clock node. The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the child div. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: fix uarts clock errorXing Zheng1-4/+4
Due to a copy-paste error the uart1 and uart2 clock div set incorrect, fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-16clk: rockchip: rk3036: fix the FLAGs for clock muxXing Zheng1-6/+6
The DFLAGS are used for the clock dividers, the CLKSEL_CON flags of COMPOSITE_NODIV type should be MFLAGS. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-01-02Merge branch 'clk-rockchip' into clk-nextMichael Turquette4-47/+116
2016-01-02clk: rockchip: fix section mismatches with new child-clocksHeiko Stübner4-47/+116
To model the muxes downstream of fractional dividers we introduced the child property, allowing to describe a direct child clock. The first implementation seems to cause section warnings, as the core clock-tree is marked as initdata while the data pointed to from the child element is not. While there may be some way to also set that missing property in the inline notation I didn't find it, so to actually fix the issue for now move the sub-definitions into separate declarations that can have their own __initdata properties. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23Merge branch 'clk-rockchip' into clk-nextMichael Turquette5-105/+235
2015-12-23clk: rockchip: rk3036: include downstream muxes into fractional dividersXing Zheng1-17/+17
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported RK3036 SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: Allow the RK3288 SPDIF clocks to change their parentSjoerd Simons1-8/+8
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: include downstream muxes into fractional dividersHeiko Stuebner2-72/+74
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported Rockchip SoCs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: handle mux dependency of fractional dividersHeiko Stuebner2-14/+142
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-21clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner7-8/+13
As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-16clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vioYakir Yang1-1/+1
ACLK_VIO is the noc bus clock for display module, display cann't read data from ddr without this clock enabled. Due to it shouldn't belong to any driver, but we need it enabled, so just mark it as the CLK_IGNORE_UNUSED flag. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-12clk: rockchip: use rk3288-efuse clock idsZhengShunQian1-2/+2
Reference the newly added efuse clock-ids in the clock-tree. Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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