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path:
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drivers
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clk
/
rockchip
/
clk-rk3036.c
Age
Commit message (
Expand
)
Author
Files
Lines
2016-03-27
clk: rockchip: release io resource when failing to init clk
Shawn Lin
1
-0
/
+1
2016-03-27
clk: rockchip: Add support for multiple clock providers
Xing Zheng
1
-5
/
+12
2016-03-27
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
Xing Zheng
1
-0
/
+3
2016-03-23
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...
Linus Torvalds
1
-26
/
+7
2016-03-16
clk: rockchip: associate SCLK_MAC_PLL and disable reparenting on rk3036
Heiko Stuebner
1
-1
/
+1
2016-03-16
clk: rockchip: associate the rk3036 HCLK_EMAC clock-id
Xing Zheng
1
-1
/
+1
2016-02-15
Merge tag 'v4.6-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/g...
Michael Turquette
1
-26
/
+7
2016-02-04
clk: rockchip: convert manually created factor clocks to the new type
Heiko Stuebner
1
-25
/
+6
2016-02-04
clk: rockchip: fix parent of hclk_vcodec on rk3036
Heiko Stuebner
1
-1
/
+1
2016-01-24
clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for hclk_vio_bus
Yakir Yang
1
-1
/
+1
2016-01-16
clk: rockchip: rk3036: rename emac ext source clock
Xing Zheng
1
-1
/
+1
2016-01-16
clk: rockchip: rk3036: fix the div offset for emac clock
Xing Zheng
1
-2
/
+2
2016-01-16
clk: rockchip: rk3036: fix uarts clock error
Xing Zheng
1
-4
/
+4
2016-01-16
clk: rockchip: rk3036: fix the FLAGs for clock mux
Xing Zheng
1
-6
/
+6
2016-01-02
Merge branch 'clk-rockchip' into clk-next
Michael Turquette
1
-10
/
+25
2016-01-02
clk: rockchip: fix section mismatches with new child-clocks
Heiko Stübner
1
-10
/
+25
2015-12-23
Merge branch 'clk-rockchip' into clk-next
Michael Turquette
1
-17
/
+17
2015-12-23
clk: rockchip: rk3036: include downstream muxes into fractional dividers
Xing Zheng
1
-17
/
+17
2015-12-21
clk: rockchip: only enter pll slow-mode directly before reboots on rk3288
Heiko Stuebner
1
-1
/
+1
2015-12-16
clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vio
Yakir Yang
1
-1
/
+1
2015-11-23
clk: rockchip: add clock controller for rk3036
Xing Zheng
1
-0
/
+478