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path: root/drivers/clk/qcom
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2015-05-30clk: qcom: Add support for NSS/GMAC clocks and resetsStephen Boyd1-1/+593
Add the NSS/GMAC clocks and the TCM clock and NSS resets. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2015-04-30clk: qcom: Fix MSM8916 gfx3d_clk_src configurationGeorgi Djakov1-1/+1
The gfx3d_clk_src parents configuration is incorrect. Fix it. Fixes: 3966fab8b6ab "clk: qcom: Add MSM8916 Global Clock Controller support" Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-30clk: qcom: Fix MSM8916 venus divider valueGeorgi Djakov1-1/+1
One of the video codec clock frequencies has incorrect divider value. Fix it. Fixes: 3966fab8b6ab "clk: qcom: Add MSM8916 Global Clock Controller support" Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-08clk: qcom: Fix parent_map translationsGeorgi Djakov2-11/+35
When we introduced the parent_map tables, we missed to update some of the functions where mapping is translated. Fix this. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Tested-by: Nicolas Dechesne <nicolas.dechesne@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-07clk: qcom: fix driver dependenciesBartlomiej Zolnierkiewicz1-0/+1
Support for Qualcomm's clock controllers should be available only on Qualcomm platforms. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-04-06clk: qcom: Add EBI2 clocks for IPQ806xArchit Taneja1-0/+32
The NAND controller within EBI2 requires EBI2_CLK and EBI2_ALWAYS_ON_CLK clocks. Create structs for these clocks so that they can be used by the NAND controller driver. Add an entry for EBI2_AON_CLK in the gcc-ipq806x DT binding document. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-26clk: qcom: fix simple_return.cocci warningsFengguang Wu1-5/+1
drivers/clk/qcom/clk-pll.c:74:1-4: WARNING: end returns can be simpified Simplify a trivial if-return sequence. Possibly combine with a preceding function call. Generated by: scripts/coccinelle/misc/simple_return.cocci Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-26clk: qcom: Fix ipq806x LCC frequency tablesStephen Boyd1-9/+9
These frequency tables list the wrong rates. Either they don't have the correct frequency at all, or they're specified in kHz instead of Hz. Fix it. Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver" Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23clk: qcom: Add MSM8916 Global Clock Controller supportGeorgi Djakov3-0/+2877
This patch adds support for the global clock controller found on the MSM8916 based devices. It allows the various device drivers to probe and control their clocks and resets. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> [sboyd@codeaurora.org: Removed NULL entry from parent_maps] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23clk: qcom: Introduce parent_map tablesGeorgi Djakov15-286/+338
In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23clk: qcom: Do some error handling in configure_bank()Georgi Djakov1-21/+42
Currently configure_bank() returns void. Add some error checking on the regmap calls and propagate if there is any error. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23clk: qcom: Fix clk_get_parent function return valueGeorgi Djakov2-9/+24
According to the common clock framework API, the clk_get_parent() function should return u8. Currently we are returning negative values on error. Fix this and use the default parent in case of an error. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-23clk: qcom: fix RCG M/N counter configurationArchit Taneja1-1/+1
Currently, a RCG's M/N counter (used for fraction division) is set to either 'bypass' (counter disabled) or 'dual edge' (counter enabled) based on whether the corresponding rcg struct has a mnd field specified and a non-zero N. In the case where M and N are the same value, the M/N counter is still enabled by code even though no division takes place. Leaving the RCG in such a state can result in improper behavior. This was observed with the DSI pixel clock RCG when M and N were both set to 1. Add an additional check (M != N) to enable the M/N counter only when it's needed for fraction division. Signed-off-by: Archit Taneja <architt@codeaurora.org> Fixes: bcd61c0f535a (clk: qcom: Add support for root clock generators (RCGs)) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-12Merge branch 'clk-fixes' into clk-nextStephen Boyd3-5/+16
2015-03-12clk: qcom: Properly change rates for ahbix clockStephen Boyd3-3/+65
The ahbix clock can never be turned off in practice. To change the rates we need to switch the mux off the M/N counter to an always on source (XO), reprogram the M/N counter to get the rate we want and finally switch back to the M/N counter. Add a new ops structure for this type of clock so that we can set the rate properly. Fixes: c99e515a92e9 "clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver" Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-03-12clk: qcom: Fix i2c frequency tableStephen Boyd1-1/+1
PXO is 25MHz, not 27MHz. Fix the table. Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Tested-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-25clk: qcom: fix platform_no_drv_owner.cocci warningskbuild test robot1-1/+0
drivers/clk/qcom/lcc-msm8960.c:577:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-25clk: qcom: fix platform_no_drv_owner.cocci warningskbuild test robot1-1/+0
drivers/clk/qcom/lcc-ipq806x.c:465:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci CC: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-25clk: qcom: Add PLL4 vote clockStephen Boyd1-0/+13
This clock is needed for most audio clock frequencies. Add it. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-25clk: qcom: lcc-msm8960: Fix PLL rate detectionStephen Boyd1-1/+1
regmap_read() returns 0 on success, not the value of the register that is read. Fix it so we properly detect the frequency plan. Fixes: b82875ee07e5 "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-25clk: qcom: Fix slimbus n and m val offsetsStephen Boyd1-2/+2
These shifts were copy/pasted from the pcm which is a different size RCG. Use the correct offsets so that slimbus rates are correct. Fixes: b82875ee07e5 "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-02clk: Add rate constraints to clocksTomeu Vizoso3-2/+15
Adds a way for clock consumers to set maximum and minimum rates. This can be used for thermal drivers to set minimum rates, or by misc. drivers to set maximum rates to assure a minimum performance level. Changes the signature of the determine_rate callback by adding the parameters min_rate and max_rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [sboyd@codeaurora.org: set req_rate in __clk_init] Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate migrated clk-private.h changes to clk.c]
2015-01-27clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driverStephen Boyd3-0/+595
Add an LCC driver for MSM8960/APQ8064 that supports the i2s, slimbus, and pcm clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: qcom: Add IPQ806X LPASS clock controller (LCC) driverRajendra Nayak4-0/+495
Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and pcm clocks. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> [sboyd@codeaurora.org: Reworded commit text, added Kconfig select, fleshed out Kconfig description a bit more, added pll4 configuration and reworked probe for it, added muxes, split out dt-binding file] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: qcom: Add simple regmap based muxesStephen Boyd3-0/+89
Add support for muxes that use regmap instead of readl/writel directly. We don't support as many features as clk-mux.c, but this is good enough to support getting and setting parents. Adding a table based lookup can be added in the future if needed. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27clk: qcom: Add support for regmap divider clocksJosh Cartwright3-0/+100
Add support for dividers that use regmap instead of readl/writel. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Switch to using generic divider code, drop enable/disable, reword commit text] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-20Merge tag 'clk-for-linus-3.19' of ↵Linus Torvalds3-20/+30
git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
2014-12-14Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds5-5/+0
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
2014-12-03clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso3-20/+30
This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17clk: qcom: Fix duplicate rbcpr clock nameGeorgi Djakov1-1/+1
There is a duplication in a clock name for apq8084 platform that causes the following warning: "RBCPR_CLK_SRC" redefined Resolve this by adding a MMSS_ prefix to this clock and making its name coherent with msm8974 platform. Fixes: 2b46cd23a5a2 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support") Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-10-20clk: qcom: drop owner assignment from platform_driversWolfram Sang5-5/+0
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-09-26Merge tag 'qcom-clocks-for-3.18' of ↵Mike Turquette9-88/+219
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next qcom clock changes for 3.18 Some fixes for the IPQ driver and some code consolidation and refactoring.
2014-09-25clk: Remove .owner field for driverKiran Padwal3-3/+0
There is no need to init .owner field. Based on the patch from Peter Griffin <peter.griffin@linaro.org> "mmc: remove .owner field for drivers using module_platform_driver" This patch removes the superflous .owner field for drivers which use the module_platform_driver API, as this is overriden in platform_driver_register anyway." Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-22clk: qcom: Add support for banked MD RCGsStephen Boyd3-56/+77
The banked MD RCGs in global clock control have a different register layout than the ones implemented in multimedia clock control. Add support for these types of clocks so we can change the rates of the UBI32 clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-22clk: qcom: Add support for setting rates on PLLsStephen Boyd2-1/+87
Some PLLs may require changing their rate at runtime. Add support for these PLLs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-22clk: qcom: Consolidate frequency finding logicStephen Boyd4-32/+27
There are two find_freq() functions in clk-rcg.c and clk-rcg2.c that are almost exactly the same. Consolidate them into one function to save on some code space. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-22clk: qcom: Add IPQ8064 PLL required for USBAndy Gross1-1/+30
This patch adds the PLL0 that is required for the USB clocks to work properly. Signed-off-by: Andy Gross <agross@codeaurora.org> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-02clk: qcom: Fix sdc 144kHz frequency entryStephen Boyd1-1/+1
The pre-divider for the sdc clocks only has 2 bits in it, so we can't possibly divide by anything larger than 4 here. Furthermore, we program the value of ~(n - m) and the n value is larger than 8 bits (max of 256). Replace this entry with 200kHz which is close enough to 144kHz to be usable. Cc: Kumar Gala <galak@codeaurora.org> Cc: Andy Gross <agross@codeaurora.org> Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global clock controller (GCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-25Merge tag 'qcom-clocks-for-3.17' of ↵Mike Turquette14-80/+10568
git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm qcom clock changes for 3.17 These patches add support for a handful of Qualcomm's SoC clock controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064. There's also a small collection of bug fixes that aren't critical -rc worthy regressions because the consumer drivers aren't present or using the buggy clocks and one optimization for HDMI.
2014-07-15clk: qcom: Add support for APQ8064 multimedia clocksStephen Boyd1-2/+431
The APQ8064 multimedia clock controller is fairly similar to the 8960 multimedia clock controller, except that gfx2d0/1 has been removed and the gfx3d frequency is slightly faster when using the newly introduced PLL15. We also add vcap clocks and a couple new TV clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: pll: Add support for configuring SR PLLsStephen Boyd2-3/+14
Some SR type PLLs need to be configured for a certain rate when linux boots. Add support for these types of PLLs so that we can program PLL15's rate on apq8064. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: mdp_lut_clk is a child of mdp_srcStephen Boyd1-1/+1
The mdp_lut_clk isn't a child of the mdp_clk. Instead it's the child of the mdp_src clock. Fix it. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: Fix PLL rate configurationsStephen Boyd3-17/+38
Sometimes we need to program PLLs with a fixed rate configuration during driver probe. Doing this after we register the PLLs with the clock framework causes the common clock framework to assume the rate of the PLLs are 0. This causes all sorts of problems for rate recalculations because the common clock framework caches the rate once at registration time unless a flag is set to always recalculate the rates. Split the qcom_cc_probe() function into two pieces, map and everything else, so that drivers which need to configure some PLL rates or otherwise twiddle bits in the clock controller can do so before registering clocks. This allows us to properly detect the rates of PLLs that are programmed at boot. Fixes: 49fc825f0cc2 "clk: qcom: Consolidate common probe code" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: Fix MN frequency tables, parent map, and jpegdStephen Boyd1-40/+42
Clocks that don't have a pre-divider don't list any pre-divider in their frequency tables, but their tables are initialized using aggregate initializers. Use tagged initializers so we properly assign the m and n values for each frequency. Furthermore, the mmcc_pxo_pll8_pll2_pll3 array improperly mapped the second element to pll2 instead of pll8, causing the clock driver to recalculate the wrong rate for any clocks using this array along with a rate that uses pll2. Plus the .num_parents field is 3 instead of 4 so you can't even switch the parent to pll3. Finally I noticed that the jpegd clock improperly indicates that the pre-divider width is only 2, when it's actually 4 bits wide. Fixes: 6d00b56fe "clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC)" Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: Support bypass RCG configurationStephen Boyd3-14/+47
In the case of HDMI clocks, we want to bypass the RCG's ability to divide the output clock and pass through the parent HDMI PLL rate. Add a simple set of clk_ops to configure the RCG to do this. This removes the need to keep adding more frequency entries to the tv_src clock whenever we want to support a new rate. Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: Add support for IPQ8064's global clock controller (GCC)Kumar Gala3-0/+2433
Add a driver for the global clock controller found on IPQ8064 based platforms. This should allow most non-multimedia device drivers to probe and control their clocks. This is currently missing clocks for USB HSIC and networking devices. Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) supportGeorgi Djakov3-0/+3362
Add support for the multimedia clock controller found on the APQ8084 based platforms. This will allow the multimedia device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> [sboyd: Rework parent mapping to avoid conflicts] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-11clk: qcom: Add APQ8084 clocks for SATA, PCIe and UFSGeorgi Djakov1-0/+667
Add the necessary clocks for SATA, PCIe and UFS to the APQ8084 global clock controller (GCC). This will allow the above device drivers to control their clocks. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-11clk: qcom: Add APQ8084 Global Clock Controller supportGeorgi Djakov3-0/+2953
This patch adds support for the global clock controller found on the APQ8084 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-11clk: qcom: Fully support apq8064 global clock controlStephen Boyd1-4/+569
Add in the handful of new clocks and introduce a new reset table with the few new resets. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 07:13:06 +0000