| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2015-03-31 | CLK: Pistachio: Register external clock gates | Andrew Bresticker | 1 | -0/+21 |
| 2015-03-31 | CLK: Pistachio: Register system interface gate clocks | Andrew Bresticker | 1 | -0/+42 |
| 2015-03-31 | CLK: Pistachio: Register peripheral clocks | Andrew Bresticker | 1 | -0/+67 |
| 2015-03-31 | CLK: Pistachio: Register core clocks | Andrew Bresticker | 2 | -0/+200 |
| 2015-03-31 | CLK: Pistachio: Add PLL driver | Andrew Bresticker | 3 | -0/+452 |
| 2015-03-31 | CLK: Add basic infrastructure for Pistachio clocks | Andrew Bresticker | 3 | -0/+265 |
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index : linux | |
| Linux Kernel (branches are rebased on master from time to time) | Linus Torvalds |
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