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2017-02-14clk: mvebu: adjust clock handling for the CP110 system controllerThomas Petazzoni1-2/+11
This commit: - makes the GOP_DP (bit 9) gatable clock a child clock of the SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit 18 was just named SD_MMC, but since it also covers the GOP block, it is renamed SD_MMC_GOP. - makes the MG (bit 5) gatable clock a child clock of the MG_CORE clock (bit 6) Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-02-10clk: mvebu: Expand mv98dx3236-core-clock supportChris Packham3-14/+181
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. Port code from the Marvell supplied Linux kernel to support different PLL frequencies and provide clock gating support. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-27clk: mvebu: support for 98DX3236 SoCChris Packham3-0/+70
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz. The clock gating options are a subset of those on the Armada XP. The core clock divider is different to the Armada XP also. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-09clk: mvebu: adjust AP806 CPU clock frequencies to production chipThomas Petazzoni1-5/+23
This commit adjusts the list of possible "Sample At Reset" values that define the CPU clock frequency of the AP806 (part of Marvell Armada 7K/8K) to the values that have been validated with the production chip. Earlier values were preliminary. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: mvebu: make ap806-system-controller explicitly non-modularPaul Gortmaker1-20/+3
The Kconfig currently controlling compilation of this code is: drivers/clk/mvebu/Kconfig:config ARMADA_AP806_SYSCON drivers/clk/mvebu/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: mvebu: make cp110-system-controller explicitly non-modularPaul Gortmaker1-32/+3
The Kconfig currently controlling compilation of this code is: drivers/clk/mvebu/Kconfig:config ARMADA_CP110_SYSCON drivers/clk/mvebu/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: mvebu: migrate CP110 system controller to clk_hw API and registrationMarcin Wojtas1-78/+72
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in Armada CP110 system controller driver. This commit introduces new API and registration for all clocks in CP110 HW blocks. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: mvebu: armada-37xx-periph: Fix the clock gate flagGregory CLEMENT1-0/+1
For the gate part of the peripheral clock setting the bit disables the clock and clearing it enables the clock. This is not the default behavior of clk_gate component, so we need to use the CLK_GATE_SET_TO_DISABLE flag. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-17clk: mvebu: armada-37xx-periph: Fix the clock provider registrationGregory CLEMENT1-5/+5
While trying using a peripheral clock on a driver, I saw that the clock pointer returned by the provider was NULL. The problem was a missing indirection. It was the pointer stored in the hws array which needed to be updated not the value it contains. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Fixes: 8ca4746a78ab ("clk: mvebu: Add the peripheral clock driver for Armada 3700") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-10-07Merge tag 'armsoc-drivers' of ↵Linus Torvalds1-0/+70
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Arnd Bergmann: "Driver updates for ARM SoCs, including a couple of newly added drivers: - The Qualcomm external bus interface 2 (EBI2), used in some of their mobile phone chips for connecting flash memory, LCD displays or other peripherals - Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for the EFUSE based on that firmware interface. - Perf support for the AppliedMicro X-Gene performance monitor unit - Reset driver for STMicroelectronics STM32 - Reset driver for SocioNext UniPhier SoCs Aside from these, there are minor updates to SoC-specific bus, clocksource, firmware, pinctrl, reset, rtc and pmic drivers" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) bus: qcom-ebi2: depend on HAS_IOMEM pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181 clk: mvebu: Add clk support for the orion5x SoC mv88f5181 dt-bindings: EXYNOS: Add Exynos5433 PMU compatible clocksource: exynos_mct: Add the support for ARM64 perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver Documentation: Add documentation for APM X-Gene SoC PMU DTS binding MAINTAINERS: Add entry for APM X-Gene SoC PMU driver bus: qcom: add EBI2 driver bus: qcom: add EBI2 device tree bindings rtc: rtc-pm8xxx: Add support for pm8018 rtc nvmem: amlogic: Add Amlogic Meson EFUSE driver firmware: Amlogic: Add secure monitor driver soc: qcom: smd: Reset rx tail rather than tx memory: atmel-sdramc: fix a possible NULL dereference reset: hi6220: allow to compile test driver on other architectures reset: zynq: add driver Kconfig option reset: sunxi: add driver Kconfig option reset: stm32: add driver Kconfig option reset: socfpga: add driver Kconfig option ...
2016-09-22clk: mvebu: dynamically allocate resources in Armada CP110 system controllerMarcin Wojtas1-9/+20
Original commit, which added support for Armada CP110 system controller used global variables for storing all clock information. It worked fine for Armada 7k SoC, with single CP110 block. After dual-CP110 Armada 8k was introduced, the data got overwritten and corrupted. This patch fixes the issue by allocating resources dynamically in the driver probe and storing it as platform drvdata. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-22clk: mvebu: fix setting unwanted flags in CP110 gate clockMarcin Wojtas1-0/+2
Armada CP110 system controller comprises its own routine responsble for registering gate clocks. Among others 'flags' field in struct clk_init_data was not set, using a random values, which may cause an unpredicted behavior. This patch fixes the problem by resetting all fields of clk_init_data before assigning values for all gated clocks of Armada 7k/8k SoCs family. Fixes: d3da3eaef7f4 ("clk: mvebu: new driver for Armada CP110 system ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> CC: <stable@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-21clk: mvebu: Add clk support for the orion5x SoC mv88f5181Jamie Lentin1-0/+70
Referring to the u-boot sources for the Netgear WNR854T, add support for the mv88f5181. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin <jm@lentin.co.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-08-24clk: mvebu: Remove redundant dev_err call in armada_3700_periph_clock_probe()Wei Yongjun1-3/+1
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: mvebu: Add the peripheral clock driver for Armada 3700Gregory CLEMENT2-0/+450
These clocks are the ones which will be used as source for the peripherals of the Armada 3700 SoC. On this SoC there is two blocks of clocks: the North bridge one and the South bridge one. Most of them are gatable. Most of the time their rate are their parent rated divided by a ratio depending of two registers. Their parent can be choose between the TBG clocks for most of them. However, some of them can't choose their parent or directly depend of the xtal clocks. Other ones do not use exactly the same pattern to find the ratio between their parent rate and their rate. For these reason each clock is a composite clock and the operations they use are different depending of the clock. According to the datasheet it would be possible to select the parent clock and the ratio, however currently the driver does not support it. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: mvebu Add the time base generator clocks for Armada 3700Gregory CLEMENT2-0/+159
These clocks are children of the xtal clock and each one can be selected as a source for the peripheral clocks. According to the datasheet it should be possible to modify their rate, but currently it is not supported. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: mvebu: Add the xtal clock for Armada 3700 SoCGregory CLEMENT3-0/+95
This clock is the parent of all the Armada 3700 clocks. It is a fixed rate clock which depends on the gpio configuration read when resetting the SoC. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-12clk: mvebu: armada-39x: add clk description for supported interfacesGrzegorz Jaszczyk1-0/+2
Both SATA and second USB3.0 interface are supported in Armada-39x SoC family. Add necessary clk description, so both xhci and sata drivers can be correctly initialized. The binding documentation has also been updated accordingly. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: mvebu: new driver for Armada CP110 system controllerThomas Petazzoni3-0/+410
The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-05-06clk: mvebu: new driver for Armada AP806 system controllerThomas Petazzoni3-0/+172
The Armada AP806 system controller, amongst other things, provides a number of clocks for the platform: the CPU cluster clocks, whose frequencies are found by reading the Sample At Reset register, one fixed clock, and another clock derived from the fixed clock, which is the one used by most peripherals in AP806. The AP806 is one of the two core HW blocks used in the Marvell 7K/8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-03-03clk: mvebu: Remove CLK_IS_ROOTStephen Boyd2-8/+6
This flag is a no-op now. Remove usage of the flag. Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25clk: mvebu: Move corediv config to mvebu configKevin Smith1-1/+0
The core clock does not depend on corediv, so enabling corediv based on the clock is not really correct. Move the corediv config option from the clock driver Kconfig to the mvebu Kconfig so that it can be enabled by the MACH option instead. This also enables corediv on Armada 375 and 38X, which was previously missing. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-02-25clk: mvebu: Remove corediv clock from Armada XPKevin Smith1-1/+0
There is no corediv clock on Armada XP, so this is unnecessary. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: move the common clock's to_clk_*(_hw) macros to clk-provider.hGeliang Tang2-4/+0
to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang <geliangtang@163.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-29clk: mvebu: Mark ioremapped memory as __iomemStephen Boyd1-1/+1
Silence the following sparse warning drivers/clk/mvebu/dove-divider.c:252:14: warning: incorrect type in assignment (different address spaces) drivers/clk/mvebu/dove-divider.c:252:14: expected void *base drivers/clk/mvebu/dove-divider.c:252:14: got void [noderef] <asn:2>* drivers/clk/mvebu/dove-divider.c:256:13: warning: incorrect type in argument 2 (different address spaces) drivers/clk/mvebu/dove-divider.c:256:13: expected void [noderef] <asn:2>*base drivers/clk/mvebu/dove-divider.c:256:13: got void *base drivers/clk/mvebu/dove-divider.c:257:25: warning: incorrect type in argument 1 (different address spaces) drivers/clk/mvebu/dove-divider.c:257:25: expected void volatile [noderef] <asn:2>*iomem_cookie drivers/clk/mvebu/dove-divider.c:257:25: got void *base Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-22clk: add Dove PLL divider support for GPU, VMeta and AXI clocksRussell King4-1/+275
Add support for the Dove PLL dividers, which are used to generate the clocks for the AXI bus, as well as the GPU and VMeta peripherals. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-10-16clk: mvebu: Use of_clk_get_parent_name()Stephen Boyd1-3/+1
This reverts commit e79b202c632f24f49f2eb9459b88b5fd9e332263. Now that we use of_clk_get() inside of_clk_get_parent_name() we can safely use it here. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-10-15Merge branch 'clk-fixes' into clk-nextStephen Boyd1-1/+3
* clk-fixes: Partially revert "clk: mvebu: Convert to clk_hw based provider APIs"
2015-10-14Partially revert "clk: mvebu: Convert to clk_hw based provider APIs"Stephen Boyd1-1/+3
This partially reverts commit eca61c9ff2588e1df373e61078e1874976315839. Thomas reports that it causes regressions on Armada XP devices. This is because of_clk_get_parent_name() relies on the property 'clock-output-names' to resolve the name of a clock's parent, without trying to get the clock from the framework and call __clk_get_name(). Given that Armada XP devices don't have the 'clock-output-names' property, of_clk_get_parent_name() returns the name of the node which doesn't match the actual parent clock's name at all, causing CPU clocks to never link up with their parents. Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-09-17clk: Remove unneeded semicolonsJavier Martinez Canillas1-1/+1
There are cleary typo errors so can be removed. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Acked-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24clk: mvebu: Convert to clk_hw based provider APIsStephen Boyd1-4/+2
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. This also removes a clk_get() in this driver that can just as easily use of_clk_get_parent_name() instead. Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: mvebu: Remove clk.h includeStephen Boyd2-2/+3
Clock provider drivers generally shouldn't include clk.h because it's the consumer API. Only include the header if necessary. The clkdev.h include isn't used here either, so drop it and add in slab.h to keep things compiling. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-18clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSEDBoris Brezillon1-1/+1
The crypto SRAM, used by the armada 370 cpuidle code to workaround a bug in the BootROM code, requires the crypto clk to be up and running. Flag the crypto clk as IGNORE_UNUSED until we add the proper infrastructure to define the crypto SRAM in the DT and reference the crypto clk in this SRAM node. Reported-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-06-03clk: mvebu: add missing CESA gate clkBoris Brezillon1-0/+1
Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock. Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-03-04clk: mvebu: add Marvell Armada 39x driverThomas Petazzoni3-0/+161
This commit adds a new clock driver for the Marvell Armada 39x family of processors. This driver is fairly similar to the ones already used on other Marvell EBU processors, with the following main differences: * Different set of ratios * Different set of core clocks * Configurable reference clock in frequency Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2015-03-04clk: mvebu: extend common code to allow an optional refclkThomas Petazzoni2-0/+18
The Armada 39x, contrary to its predecessor, has a configurable reference clock frequency, of either 25 Mhz, or 40 Mhz. For the previous SoCs, it was fixed to 25 Mhz and described directly as such in the Device Tree. For Armada 39x, we need to read certain registers to know whether the frequency is 25 or 40 Mhz. Therefore, this commit extends the common mvebu clock code to allow the SoC-specific code to say it wants to register a reference clock, by giving a non-NULL ->get_refclk_freq() function pointer in its coreclk_soc_desc structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2014-11-30clk: mvebu: add suspend/resume for gatable clocksThomas Petazzoni1-2/+30
This commit adds suspend/resume support for the gatable clock driver used on Marvell EBU platforms. When getting out of suspend, the Marvell EBU platforms go through the bootloader, which re-enables all gatable clocks. However, upon resume, the clock framework will not disable again all gatable clocks that are not used. Therefore, if the clock driver does not save/restore the state of the gatable clocks, all gatable clocks that are not claimed by any device driver will remain enabled after a resume. This is why this driver saves and restores the state of those clocks. Since clocks aren't real devices, we don't have the normal ->suspend() and ->resume() of the device model, and have to use the ->suspend() and ->resume() hooks of the syscore_ops mechanism. This mechanism has the unfortunate idea of not providing a way of passing private data, which requires us to change the driver to make the assumption that there is only once instance of the gatable clock control structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-kernel@vger.kernel.org Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-10-03Merge tag 'clk-mvebu-3.18-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2-5/+5
clk-next clock mvebu changes for v3.18 (round 2) - armada 370/375 - Fix SSCG node lookup
2014-09-26Merge tag 'clk-mvebu-3.18' of git://git.infradead.org/linux-mvebu into clk-nextMike Turquette4-2/+99
clock changes for mvebu for v3.18 - correct timer drift caused by SSCG deviation - fix typo in comment
2014-09-16clk: mvebu: fix sscg node lookupThomas Petazzoni2-5/+5
Commit 15917b16022427c53755abff4dc7051f3076dd7a ("clk: mvebu: Fix clk frequency value if SSCG is enabled") introduced some logic in the common mvebu clock code to adjust the clock frequency according to the configuration of the SSCG. In order to do this, it looks up for a DT node called "sscg" and maps it before accessing the SSCG configuration register. However, the lookup is currently done using: sscg_np = of_find_node_by_name(np, "sscg"); where "np" is a pointer to the DT node of the clock for which we are calculating the adjusted frequency. This means that if the "sscg" node is *after* the clock node in the Device Tree, it works fine (and that's the case for Armada 370). However, if it turns out that the "sscg" node is *before* the clock node in the Device Tree, it won't work because the sscg node will not be found. What we really want here is a search of the entire Device Tree, not only starting from the clock node, so instead of passing "np" as first argument of of_find_node_by_name(), we simply need to pass NULL. Passing a non-NULL argument is typically used in a loop, so that the search for the next matching node starts right after the node that was matched. This makes the "np" argument to the kirkwood_fix_sscg_deviation() function unnecessary, which leads to further cleanups. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Fixes: 15917b1602242 ("clk: mvebu: Fix clk frequency value if SSCG is enabled") Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1410880503-2322-1-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-09clk: mvebu: armada-375: Fix the description of the SAR in the commentGregory CLEMENT1-2/+2
For dealing with the code we use the SAR1 and not the SAR0. The code was correct, and now the comments too. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Leigh Brown <leigh@solinno.co.uk> Link: https://lkml.kernel.org/r/1409645719-20003-5-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-09clk: mvebu: armada-370: Fix timer drift caused by the SSCG deviationGregory CLEMENT1-0/+8
This commit activates the SSCG deviation correction for the Armada 370. It uses the optional function introduced by the commit "clk: mvebu: Fix clk frequency value if SSCG is enabled". Without this fix the deviation measured on a Mirabox was of a few second each hour, whereas with this fix it was reduced at around 50ppm (around 4s per day). Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Leigh Brown <leigh@solinno.co.uk> Link: https://lkml.kernel.org/r/1409645719-20003-3-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-09clk: mvebu: Fix clk frequency value if SSCG is enabledGregory CLEMENT2-0/+89
When the SSCG (Spread Spectrum Clock Generator) is enabled, it shifts the frequency of the clock. The percentage is no more than 1% but when the clock is used for a timer it leads to a clock drift. This patch allows to correct the affected clock when the SSCG is enabled. The check is done in an new optional function related to each SoC: is_sscg_enabled(). The fix is done with the other new optional function related to each SoC: fix_sscg_deviation. If one these functions are not present then no correction is done on the clock frequency. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Leigh Brown <leigh@solinno.co.uk> Link: https://lkml.kernel.org/r/1409645719-20003-2-git-send-email-gregory.clement@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-02cpufreq: kirkwood: use the powersave multiplexerMike Turquette1-2/+13
The powersave clock acts like a multiplexer for the cpu, selecting either the clock signal derived from the cpu pll or from the ddr clock. This patch changes powersave from a gate clock to a mux clock to better reflect this behavior. This is a cleaner approach whereby the frequency of the cpu always matches the rate of powersave_clk. The cpufreq driver for the kirkwood platform no longer must parse this behavior out of various calls to clk_enable and clk_disable, but can instead simply select the parent cpu it wants when changing rate. Likewise when requesting the cpu rate we need only query powersave_clk's rate through the usual call to clk_get_rate. The new clock data and corresponding changes to the cpufreq driver are combined into this single commit to avoid a git bisect issue where this cpufreq driver fails to work properly between the commit that updates the kirkwood clock driver and the commit that changes how the cpufreq driver uses that clock. Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Tested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-01clk: mvebu: powersave clock is a multiplexerMike Turquette1-0/+87
Kirkwood is unique among the mvebu SoCs for having a clock multiplexer that feeds into the cpu. This multiplexer can select either the cpu pll or the ddr clock as its input signal, allowing for a choice between performance and power savings. This patch introduces the code needed to register the clock multiplexer on Kirkwood SoCs but does not include the clock data to actually register the clock. That will be done in a follow-up patch which is necessary to prevent breaking git bisect. Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-01clk: mvebu: share locks between gate clocksMike Turquette2-3/+8
Refactor mvebu_clk_gating_setup() to use a common spinlock instead of a unique lock for every instance of a struct clk_gating_ctrl object. This will be used later for a separate mux clock type that shares a register with gate clock types and needs to use the same lock to protect access to the register. Cc: Andrew Lunn <andrew@lunn.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-16clk: mvebu: extend clk-cpu for dynamic frequency scalingThomas Petazzoni1-5/+75
This commit extends the existing clk-cpu driver used on Marvell Armada XP platforms to support the dynamic frequency scaling of the CPU clock. Non-dynamic frequency change was already supported (and used before secondary CPUs are started), but the dynamic frequency change requires a completely different procedure. In order to achieve this, the clk_cpu_set_rate() function is reworked to handle two separate cases: - The case where the clock is enabled, which is the new dynamic frequency change code, implemented in clk_cpu_on_set_rate(). This part will be used for cpufreq activities. - The case where the clock is disabled, which is the existing frequency change code, moved in clk_cpu_off_set_rate(). This part is already used to set the clock frequency of the secondary CPUs before starting them. In order to implement the dynamic frequency change function, we need to access the PMU DFS registers, which are outside the currently mapped "Clock Complex" registers, so a new area of registers is now mapped. This affects the Device Tree binding, but we are careful to do it in a backward-compatible way (by allowing the second pair of registers to be non-existent, and in this case, ensuring clk_cpu_on_set_rate() returns an error). Note that technically speaking, the clk_cpu_on_set_rate() does not do the entire procedure needed to change the frequency dynamically, as it involves touching a number of PMSU registers. This is done through a clock notifier registered by the PMSU driver in followup commits. Cc: <devicetree@vger.kernel.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1404920715-19834-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-26clk: mvebu: add Orion5x clock driverThomas Petazzoni3-0/+215
This commit adds a core clock driver for the Orion5x SoC, with support for the tclk, the CPU frequency and the DDR frequency. All the details about the Sample-At-Reset register were extracted from the U-Boot sources for Orion5x. Note that Orion5x does not have gatable clocks, so this core clock driver is sufficient to support clocking on Orion5x platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1398202002-28530-5-git-send-email-thomas.petazzoni@free-electrons.com Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-03-18Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette1-1/+24
clk-next-mvebu clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
2014-03-13clk: mvebu: Support Armada 380 SoC on the core divider clockEzequiel Garcia1-0/+23
This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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