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path: root/drivers/clk/mmp/clk-of-mmp2.c
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2020-10-13clk: mmp2: Fix the display clock divider baseLubomir Rintel1-2/+2
The LCD clock dividers are apparently based on one. No datasheet, determined empirically, but seems to be confirmed by line 19 of lcd.fth in OLPC laptop's Open Firmware [1]: h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz [1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: mmp2: Add support for power islandsLubomir Rintel1-0/+42
Apart from the clocks and resets, the PMU hardware also controls power to peripherals that are on separate power islands. On MMP2, that's the GC860 GPU and the SSPA audio interface, while on MMP3 also the camera interface is on a separate island, along with the pair of GC2000 and GC300 GPUs and the SSPA. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-12-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: mmp2: Add the audio clockLubomir Rintel1-0/+4
This clocks the Audio block. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-9-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: mmp2: Add the I2S clocksLubomir Rintel1-0/+46
A pair of fractional clock sources for PLLs and gates. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-8-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()Lubomir Rintel1-2/+2
This is a trivial rename for a routine that registers more clock sources than the PLLs -- there's also a XO. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-7-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: mmp2: Move thermal register defines up a bitLubomir Rintel1-4/+4
A trivial change to keep the sorting sane. The APBC registers are happier when they are grouped together, instead of mixed with the APMU ones. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200519224151.2074597-6-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: Fix bit masks for LCDC I/O and pixel clocksLubomir Rintel1-2/+2
They were reversed because I read the datasheet upside down. Actually there is no datasheet, but I ended up understanding the comments in Open Firmware driver wrong. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-18-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: Add clock for fifth SD HCI on MMP3Lubomir Rintel1-0/+2
There's one extra SDHCI on MMP3, used by the internal SD card on OLPC XO-4. Add a clock for it. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-17-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: Add clocks for the thermal sensorsLubomir Rintel1-0/+16
The register definitions gotten from OLPC Open Firmware. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-15-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: add the GPU clocksLubomir Rintel1-0/+61
MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300. On both platforms there's an AXI bus interface clock that's common for all GPUs and each GPU core has a separate clock. Meaning of the relevant APMU_GPU bits were gotten from James Cameron's message and [1], the OLPC OS kernel source [2] and Marvell's MMP3 tree. [1] http://lists.laptop.org/pipermail/devel/2019-April/039053.html [2] http://dev.laptop.org/git/olpc-kernel/commit/arch/arm/mach-mmp/mmp2.c?h=arm-3.0-wip&id=8ce9f6122 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-13-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: Add PLLs that are available on MMP3Lubomir Rintel1-7/+27
There are more PLLs on MMP3 and are configured slightly differently. Tested on a MMP3-based Dell Wyse 3020 machine. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-10-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: Check for MMP3Lubomir Rintel1-0/+12
The MMP3's are similar enough to MMP2, but there are differencies, such are more clocks available on the newer model. We want to tell which platform are we on. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-8-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: Stop pretending PLL outputs are constantLubomir Rintel1-2/+14
The hardcoded values for PLL1 and PLL2 are wrong. PLL1 is slightly off -- it defaults to 797.33 MHz, not 800 MHz. PLL2 is disabled by default, but also configurable. Tested on a MMP2-based OLPC XO-1.75 laptop, with PLL1=797.33 and various values of PLL2 set via set-pll2-520mhz, set-pll2-910mhz and set-pll2-988mhz Open Firmware words. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-6-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-03-20clk: mmp2: Constify some stringsLubomir Rintel1-6/+7
All the parent clock names for the muxes are constant. Add const. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lkml.kernel.org/r/20200309194254.29009-3-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-02-08Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+6
Pull ARM Device-tree updates from Olof Johansson: "New SoCs: - Atmel/Microchip SAM9X60 (ARM926 SoC) - OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants of it with different GPU/media IP configurations. - ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU) - ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500) - Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem) - Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class) New boards: - Allwinner: + Emlid Neutis SoM (H3 variant) + Libre Computer ALL-H3-IT + PineH64 Model B - Amlogic: + Libretech Amlogic GX PC (s905d and s912-based variants) - Atmel/Microchip: + Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1) - Marvell: + Armada 385-based SolidRun Clearfog GTR - NXP: + Gateworks GW59xx boards based on i.MX6/6Q/6QDL + Tolino Shine 3 eBook reader (i.MX6sl) + Embedded Artists COM (i.MX7ULP) + SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems) + Google Coral Edge TPU (i.MX8MQ) - Rockchip: + Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs) + Radxa Rock Pi N10 (RK3399Pro-based) + VMARC RK3399Pro SOM - ST: + Reference boards for stm32mp15 - ST Ericsson: + Samsung Galaxy S III mini (GT-I8190) + HREF520 reference board for DB8520 - TI OMAP: + Gen1 Amazon Echo (OMAP3630-based) - Qualcomm: + Inforce 6640 Single Board Computer (msm8996-based) + SC7180 IDP (SC7180-based)" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits) dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera arm64: dts: ti: k3-am65-main Add CAL node arm64: dts: ti: k3-j721e-main: Add McASP nodes arm64: dts: ti: k3-am654-main: Add McASP nodes arm64: dts: ti: k3-j721e: DMA support arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS arm64: dts: ti: k3-am65: DMA support arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss arm64: dts: ti: k3-am65-main: Correct main NAVSS representation ARM: dts: aspeed: rainier: Add UCD90320 power sequencer ARM: dts: aspeed: rainier: Switch PSUs to unknown version arm64: dts: rockchip: Kill off "simple-panel" compatibles ARM: dts: rockchip: Kill off "simple-panel" compatibles arm64: dts: rockchip: rename dwmmc node names to mmc ARM: dts: rockchip: rename dwmmc node names to mmc arm64: dts: exynos: Rename Samsung and Exynos to lowercase arm64: dts: uniphier: add reset-names to NAND controller node ...
2020-01-06clk: mmp2: Add HSIC clocksLubomir Rintel1-0/+6
There are two USB HSIC controllers on MMP2 and MMP3. Link: https://lore.kernel.org/r/20191220065314.237624-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06clk: mmp2: Fix the order of timer mux parentsLubomir Rintel1-1/+1
Determined empirically, no documentation is available. The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing what is going on, ended up just dividing the rate as of commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")' Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-02-21clk: mmp2: separate LCDC peripheral clk form the display clockLubomir Rintel1-2/+3
These are in fact two clocks, they shouldn't be exposed as one. One is required for accessing LCD controller registers (peripheral clock), while other (AXI clock) can be optionally used as a pixel clock source for the panel. LCDC can alternatively use different clocks than the Display 1 AXI clock for generating the pixel clock: the second AXI clock (fixed in this commit too), the HDMI PLL, or the AXI bus clock. They should really be controlled independently. Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24Revert "clk: mmp2: add SP clock"Lubomir Rintel1-4/+0
It seems that the kernel has no business managing this clock: once the SP clock is disabled, it's not sufficient to just enable in order to bring the SP core back up. Just let the firmware keep it enabled and don't expose it to drivers. This reverts commit fc27c2394d96fd19854b7e2d3f0e60df0d86fc90. Link: https://lore.kernel.org/lkml/154783267051.169631.3197836544646625747@swboyd.mtv.corp.google.com/ Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-02Merge branch 'for-linus' of ↵Linus Torvalds1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input Pull input updates from Dmitry Torokhov: "A tiny pull request this merge window unfortunately, should get more material in for the next release: - new driver for Raspberry Pi's touchscreen (firmware interface) - miscellaneous input driver fixes" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Input: elan_i2c - add ACPI ID for touchpad in ASUS Aspire F5-573G Input: atmel_mxt_ts - don't try to free unallocated kernel memory Input: drv2667 - fix indentation issues Input: touchscreen - fix coding style issue Input: add official Raspberry Pi's touchscreen driver Input: nomadik-ske-keypad - fix a loop timeout test Input: rotary-encoder - don't log EPROBE_DEFER to kernel log Input: olpc_apsp - remove set but not used variable 'np' Input: olpc_apsp - enable the SP clock Input: olpc_apsp - check FIFO status on open(), not probe() Input: olpc_apsp - drop CONFIG_OLPC dependency clk: mmp2: add SP clock dt-bindings: marvell,mmp2: Add clock id for the SP clock Input: ad7879 - drop platform data support
2018-11-15clk: mmp2: add SP clockLubomir Rintel1-0/+4
The "security processor", sometimes referred to as "wireless trusted module" or "generic encrypt unit" is a low-power core present on MMP2, that has nothing to do with security, wireless, trust or encryption. On an OLPC machine it runs CForth and serves as a keyboard controller: http://dev.laptop.org/git/users/wmb/cforth/tree/src/app/arm-xo-1.75/ps2.fth The register address was obtained from the OLPC kernel, since the datasheet seems to be the Marvell's most important business secret. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2018-10-17clk: mmp2: fix the clock id for sdh2_clk and sdh3_clkLubomir Rintel1-2/+2
A typo that makes it impossible to get the correct clocks for MMP2_CLK_SDH2 and MMP2_CLK_SDH3. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2016-12-08clk:mmp:clk-of-mmp2: Free memory and Unmap region obtained by kzalloc and ↵Arvind Yadav1-3/+12
of_iomap Free memory and memory mapping , if mmp2_clk_init is not successful. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> [sboyd@codeaurora.org: Put return at the right place] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-01clk: mmp: mmp2: fix return value check in mmp2_clk_init()Wei Yongjun1-1/+1
Fix the retrn value check which testing the wrong variable in mmp2_clk_init(). Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-04-15clk: mmp: Remove CLK_IS_ROOTStephen Boyd1-5/+5
This flag is a no-op now. Remove usage of the flag. Cc: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04clk: mmp: add timer clock for pxa168/mmp2/pxa910Chao Xie1-0/+6
Timer has external fast clock, and it is a mux clock. Add the timer clock type for timer driver. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04clk: mmp: Fix the wrong factor table for uart PLLChao Xie1-3/+1
The suggested value in the mmp2 manual is wrong. There are only 13 bits for numerator, but some suggested value has 14 bits. Fix the factor tabled and remove the unused items. Signed-off-by: Chao Xie <chao.xie@marvell.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-11-12clk: mmp: add mmp2 DT support for clock driverChao Xie1-0/+334
It adds the DT support for mmp2 clock subsystem. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-24 09:36:48 +0000