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path: root/drivers/clk/meson
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2021-02-09clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel2-4/+0
2021-01-04clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl1-40/+5
2021-01-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl1-2/+3
2021-01-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl1-1/+2
2021-01-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl1-1/+1
2020-12-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds11-61/+1004
2020-11-26clk: meson: g12a: add MIPI DSI Host Pixel ClockNeil Armstrong2-1/+76
2020-11-23clk: meson: enable building as modulesKevin Hilman9-9/+34
2020-11-23clk: meson: Kconfig: fix dependency for G12AKevin Hilman1-0/+1
2020-11-23clk: meson: axg: add MIPI DSI Host clockNeil Armstrong2-1/+69
2020-11-23clk: meson: axg: add Video ClocksNeil Armstrong2-1/+773
2020-11-14clk: meson: g12: use devm variant to register notifiersJerome Brunet1-14/+20
2020-11-14clk: meson: g12: drop use of __clk_lookup()Jerome Brunet1-36/+32
2020-10-28clk: define to_clk_regmap() as inline functionArnd Bergmann1-1/+4
2020-10-20Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ...Stephen Boyd1-1/+1
2020-10-13clk: meson: use semicolons rather than commas to separate statementsJulia Lawall1-1/+1
2020-09-10clk: meson: make shipped controller configurableJerome Brunet1-9/+17
2020-08-29clk: meson: g12a: mark fclk_div2 as criticalStefan Agner1-0/+11
2020-08-17clk: meson: axg-audio: fix g12a tdmout sclk inverterJerome Brunet1-25/+60
2020-08-17clk: meson: axg-audio: separate axg and g12a regmap tablesJerome Brunet1-8/+127
2020-08-17clk: meson: add sclk-ws driverJerome Brunet2-0/+62
2020-07-21Merge branch 'clk-amlogic' into clk-nextStephen Boyd4-19/+178
2020-07-10Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov1-1/+1
2020-07-09clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl2-6/+27
2020-07-09clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl2-6/+27
2020-06-24clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl1-7/+0
2020-06-19clk: meson: g12a: Add support for NNA CLK source clocksDmitry Shmidt2-1/+125
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2-0/+13
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl1-3/+11
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl1-5/+5
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl1-23/+56
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl1-1/+1
2020-04-16clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl1-8/+22
2020-04-16clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl1-18/+22
2020-04-14clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl1-3/+3
2020-04-14clk: meson8b: export the HDMI system clockMartin Blumenstingl1-1/+0
2020-02-21clk: meson: meson8b: set audio output clock hierarchyMartin Blumenstingl1-8/+13
2020-02-19clk: meson: g12a: add support for the SPICC SCLK Source clocksNeil Armstrong2-1/+134
2020-02-13clk: meson: gxbb: set audio output clock hierarchyJerome Brunet1-8/+10
2020-02-13clk: meson: gxbb: add the gxl internal dac gateJerome Brunet2-1/+4
2020-01-31Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo...Stephen Boyd5-56/+229
2020-01-07clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl1-4/+7
2019-12-23clk: let init callback return an error codeJerome Brunet4-4/+12
2019-12-16Merge branch 'v5.5/fixes' into v5.6/driversJerome Brunet2-0/+10
2019-12-16clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel1-0/+9
2019-12-16clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet1-0/+1
2019-12-11clk: meson: meson8b: use of_clk_hw_register to register the clocksMartin Blumenstingl1-1/+1
2019-12-11clk: meson: meson8b: don't register the XTAL clock when provided via OFMartin Blumenstingl1-3/+9
2019-12-11clk: meson: meson8b: change references to the XTAL clock to use [fw_]nameMartin Blumenstingl1-34/+44
2019-12-11clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifierMartin Blumenstingl1-13/+8