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path: root/drivers/clk/meson/meson8b.c
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2021-01-04clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl1-40/+5
2020-07-09clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl1-5/+25
2020-07-09clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl1-5/+25
2020-06-24clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl1-7/+0
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl1-0/+9
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl1-3/+11
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl1-5/+5
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl1-23/+56
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl1-1/+1
2020-04-14clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl1-3/+3
2020-02-21clk: meson: meson8b: set audio output clock hierarchyMartin Blumenstingl1-8/+13
2020-01-07clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl1-4/+7
2019-12-11clk: meson: meson8b: use of_clk_hw_register to register the clocksMartin Blumenstingl1-1/+1
2019-12-11clk: meson: meson8b: don't register the XTAL clock when provided via OFMartin Blumenstingl1-3/+9
2019-12-11clk: meson: meson8b: change references to the XTAL clock to use [fw_]nameMartin Blumenstingl1-34/+44
2019-12-11clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifierMartin Blumenstingl1-13/+8
2019-07-29clk: meson: clk-regmap: migrate to new parent description methodAlexandre Mergnat1-0/+3
2019-07-29clk: meson: meson8b: migrate to the new parent description methodAlexandre Mergnat1-211/+496
2019-06-11clk: meson: meson8b: add the cts_i958 clockMartin Blumenstingl1-0/+24
2019-06-11clk: meson: meson8b: add the cts_mclk_i958 clocksMartin Blumenstingl1-0/+65
2019-06-11clk: meson: meson8b: add the cts_amclk clocksMartin Blumenstingl1-0/+65
2019-05-20clk: meson: meson8b: fix a typo in the VPU parent names array variableMartin Blumenstingl1-5/+5
2019-04-01clk: meson: meson8b: add the video decoder clock treesMartin Blumenstingl1-0/+312
2019-04-01clk: meson: meson8b: add the VPU clock treesMartin Blumenstingl1-0/+167
2019-04-01clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2Martin Blumenstingl1-0/+62
2019-04-01clk: meson: meson8b: use a separate clock table for Meson8m2Martin Blumenstingl1-1/+192
2019-02-13clk: meson: meson8b: fix the naming of the APB clocksMartin Blumenstingl1-13/+13
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet1-1/+2
2019-01-07clk: meson: meson8b: add the GPU clock treeMartin Blumenstingl1-0/+146
2019-01-07clk: meson: meson8b: use a separate clock table for Meson8Martin Blumenstingl1-6/+197
2018-12-03clk: meson: meson8b: add the read-only video clock treesMartin Blumenstingl1-8/+731
2018-12-03clk: meson: meson8b: add the fractional divider for vid_pll_dcoMartin Blumenstingl1-0/+5
2018-12-03clk: meson: meson8b: fix the offset of vid_pll_dco's N valueMartin Blumenstingl1-1/+1
2018-11-23clk: meson: meson8b: add the CPU clock post divider clocksMartin Blumenstingl1-0/+244
2018-11-23clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3Martin Blumenstingl1-10/+10
2018-11-23clk: meson: meson8b: allow changing the CPU clock treeMartin Blumenstingl1-6/+6
2018-11-23clk: meson: meson8b: run from the XTAL when changing the CPU frequencyMartin Blumenstingl1-0/+63
2018-11-23clk: meson: meson8b: add support for more M/N values in sys_pllMartin Blumenstingl1-0/+5
2018-11-23clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICALMartin Blumenstingl1-1/+2
2018-11-23clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_selMartin Blumenstingl1-2/+9
2018-11-23clk: meson: meson8b: fix the width of the cpu_scale_div clockMartin Blumenstingl1-1/+1
2018-11-23clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_tableMartin Blumenstingl1-7/+8
2018-11-23clk: meson: meson8b: use the HHI syscon if availableMartin Blumenstingl1-9/+15
2018-09-26clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl1-7/+6
2018-09-26clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl1-60/+34
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet1-17/+17
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet1-73/+78
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet1-3/+0
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet1-0/+15
2018-06-09Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-15/+62