Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-03-13 | clk: meson: add fdiv clock gates | Jerome Brunet | 1 | -1/+6 |
2018-03-13 | clk: meson: add mpll pre-divider | Jerome Brunet | 1 | -1/+2 |
2018-03-13 | clk: meson: axg: add hifi pll clock | Jerome Brunet | 1 | -1/+1 |
2018-03-13 | clk: meson: split divider and gate part of mpll | Jerome Brunet | 1 | -1/+5 |
2017-12-14 | clk: meson-axg: add clock controller drivers | Qiufang Dai | 1 | -0/+126 |