linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2016-03-29	clk: mediatek: Make reset_control_ops const	Philipp Zabel	1	-1/+1
2016-03-02	clk: mediatek: Remove CLK_IS_ROOT	Stephen Boyd	1	-2/+2
2016-01-29	clk: mediatek: Fix memory leak on clock init fail	James Liao	1	-2/+4
2016-01-29	clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h	Geliang Tang	2	-5/+5
2015-10-01	clk: mediatek: Add USB clock support in MT8173 APMIXEDSYS	James Liao	5	-7/+159
2015-10-01	clk: mediatek: Add subsystem clocks of MT8173	James Liao	1	-0/+267
2015-10-01	clk: mediatek: Fix rate and dependency of MT8173 clocks	James Liao	1	-6/+13
2015-10-01	clk: mediatek: Add fixed clocks support for Mediatek SoC.	James Liao	2	-0/+40
2015-10-01	clk: mediatek: Add __initdata and __init for data and functions	James Liao	3	-10/+11
2015-10-01	clk: mediatek: Remove unused code from MT8173.	James Liao	2	-4/+2
2015-10-01	clk: mediatek: Removed unused dpi_ck clock from MT8173	James Liao	1	-1/+0
2015-10-01	clk: mediatek: add 13mhz clock for MT8173	Joe.C	1	-0/+5
2015-07-28	Merge branch 'cleanup-clk-h-includes' into clk-next	Stephen Boyd	4	-2/+6
2015-07-28	clk: mediatek: Add MT8173 MMPLL change rate support	James Liao	3	-6/+42
2015-07-28	clk: mediatek: Fix calculation of PLL rate settings	James Liao	1	-2/+2
2015-07-28	clk: mediatek: Fix PLL registers setting flow	James Liao	1	-9/+12
2015-07-20	clk: mediatek: Properly include clk.h	Stephen Boyd	4	-2/+6
2015-07-06	clk: mediatek: mt8173: Fix enabling of critical clocks	Sascha Hauer	1	-5/+21
2015-06-04	clk: mediatek: Fix apmixedsys clock registration	James Liao	2	-2/+2
2015-05-19	clk: mediatek: Initialize clk_init_data	Ricky Liang	2	-2/+2
2015-05-05	clk: mediatek: Add basic clocks for Mediatek MT8173.	James Liao	2	-0/+831
2015-05-05	clk: mediatek: Add basic clocks for Mediatek MT8135.	James Liao	2	-0/+645
2015-05-05	clk: mediatek: Add reset controller support	Sascha Hauer	3	-0/+108
2015-05-05	clk: mediatek: Add initial common clock support for Mediatek SoCs.	James Liao	6	-0/+898