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2019-03-08Merge branches 'clk-imx', 'clk-samsung', 'clk-ti', 'clk-uniphier-gear' and ↵Stephen Boyd12-256/+1770
'clk-mmp2-lcdc' into clk-next - Split LCDC into two clks on the Marvell MMP2 SoC * clk-imx: clk: imx8mq: add GPIO clocks to clock tree clk: imx: Refactor entire sccg pll clk clk: imx: scu: add cpu frequency scaling support clk: imx: imx8mm: Mark init function __init clk: imx8mq: Add the missing ARM clock dt-bindings: imx8mq-clock: Add the missing ARM clock clk: imx: imx8mq: Fix the rate propagation for arm pll clk: imx8mq: Add support for the CLKO1 clock clk: imx8mq: Fix the CLKO2 source select list clk: imx8mq: Add missing M4 clocks clk: imx: Add clock driver support for imx8mm dt-bindings: imx: Add clock binding doc for imx8mm clk: imx: Add PLLs driver for imx8mm soc clk: imx5: add imx5_SCC2_IPG_GATE clk: imx: scu: add set parent support clk: imx: scu: add fallback compatible string support clk: imx8mq: Make parent names arrays const pointers clk: imx: Make parents const pointer in mux wrappers clk: imx: Make parent_names const pointer in composite-8m * clk-samsung: clk: samsung: s3c2443: Mark expected switch fall-through clk: samsung: exynos5: Fix kfree() of const memory on setting driver_override clk: samsung: exynos5: Fix possible NULL pointer exception on platform_device_alloc() failure clk: samsung: exynos5433: Add selected IMEM clocks clk: samsung: dt-bindings: Document Exynos5433 IMEM CMU clk: samsung: exynos5433: Fix name typo in sssx clk: samsung: exynos5433: Fix definition of CLK_ACLK_IMEM_{200, 266} clocks clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDs * clk-ti: clk: clk-twl6040: Fix imprecise external abort for pdmclk ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that clk: ti: check clock type before doing autoidle ops clk: ti: add a usecount for autoidle clk: ti: generalize the init sequence of clk_hw_omap clocks clk: ti: remove usage of CLK_IS_BASIC clk: ti: add new API for checking if a provided clock is an OMAP clock clk: ti: move clk_hw_omap list handling under generic part of the driver * clk-uniphier-gear: clk: uniphier: Fix update register for CPU-gear * clk-mmp2-lcdc: clk: mmp2: separate LCDC peripheral clk form the display clock dt-bindings: marvell,mmp2: Add clock id for the LCDC clock
2019-03-08Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', ↵Stephen Boyd5-8/+12
'clk-socfpga-parent' and 'clk-struct-size' into clk-next - Various DT of_node refcount fixes - Support for fixed rate clks populated from an MMIO register - Remove clps711x driver as the board support is gone * clk-of-refcount: clk: dove: fix refcount leak in dove_clk_init() clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init() clk: armada-xp: fix refcount leak in axp_clk_init() clk: kirkwood: fix refcount leak in kirkwood_clk_init() clk: armada-370: fix refcount leak in a370_clk_init() clk: vf610: fix refcount leak in vf610_clocks_init() clk: imx7d: fix refcount leak in imx7d_clocks_init() clk: imx6sx: fix refcount leak in imx6sx_clocks_init() clk: imx6q: fix refcount leak in imx6q_clocks_init() clk: samsung: exynos4: fix refcount leak in exynos4_get_xom() clk: socfpga: fix refcount leak clk: ti: fix refcount leak in ti_dt_clocks_register() clk: qoriq: fix refcount leak in clockgen_init() clk: highbank: fix refcount leak in hb_clk_init() * clk-mmio-fixed-clock: clk: Add Fixed MMIO clock driver dt-bindings: clk: Add bindings for Fixed MMIO clock * clk-remove-clps: clk: clps711x: Remove board support * clk-socfpga-parent: clk: socfpga: Don't have get_parent for single parent ops * clk-struct-size: clk: imx: imx7ulp: use struct_size() in kzalloc()
2019-02-28clk: imx8mq: add GPIO clocks to clock treeAnson Huang1-0/+5
i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-26clk: imx: Refactor entire sccg pll clkAbel Vesa3-159/+417
Make the entire combination of plls to be one single clock. The parents used for bypasses are specified each as an index in the parents list. The determine_rate does a lookup throughout all the possible combinations for all the divs and returns the best possible 'setup' which in turn is used by set_rate later to set up all the divs and bypasses. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-26clk: imx: scu: add cpu frequency scaling supportAnson Huang1-0/+36
On NXP's i.MX SoCs with system controller inside, CPU frequency scaling can ONLY be done by system controller firmware, and it can ONLY be requested from secure mode, so Linux kernel has to call ARM SMC to trap to ARM-Trusted-Firmware to request system controller firmware to do CPU frequency scaling. This patch adds i.MX system controller CPU frequency scaling support, it reuses cpufreq-dt driver and implement the CPU frequency scaling inside SCU clock driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: imx8mm: Mark init function __initStephen Boyd1-1/+1
It calls another __init marked function and thus causes a section mismatch if we don't mark it this way. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Add the missing ARM clockAbel Vesa1-0/+6
Add the ARM clock as imx_clk_cpu type. Will be used by cpufreq. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: imx8mq: Fix the rate propagation for arm pllAbel Vesa1-1/+1
The arm pll bypass needs to propagate the rate upwards in order for the cpufreq to work. Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Add support for the CLKO1 clockFabio Estevam1-0/+3
Add the entry for the CLKO1 clock. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Fix the CLKO2 source select listFabio Estevam1-2/+2
The CLKO2 clock source select list is the following as per the i.MX8M Reference Manual: 000 - 25M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL1_DIV2 011 - SYSTEM_PLL2_DIV6 100 - SYSTEM_PLL3_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL1_CLK 111 - 32K_REF_CLK However, in imx8mq_clko2_sels[] only the first four entries are correct. Fix it by adding the missing "sys3_pll2_out" entry in order to match the description from the manual. Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: Rogerio Pimentel <rogerio.silva@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Add missing M4 clocksCarlo Caione1-0/+7
The clocks list is missing the clocks for the M4 core. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Add clock driver support for imx8mmBai Ping3-0/+682
Add clock driver support for i.MX8MM SOC. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Add PLLs driver for imx8mm socBai Ping3-1/+418
New PLLs are introduced on i.MX8M Mini SOC. PLL1416X is Integer PLL, PLL1443X is a Frac PLL. Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx5: add imx5_SCC2_IPG_GATEMichael Grzeschik1-0/+1
This adds the missing clock for the SCC2 peripheral unit. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: scu: add set parent supportAisheng Dong2-3/+100
Add clk scu set parents support. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Remove le32_to_cpu() on get_parent op] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: scu: add fallback compatible string supportAisheng Dong1-0/+1
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Make the driver support "fsl,scu-clk" fallback compatible string to allow other SoCs to reuse the common part. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx8mq: Make parent names arrays const pointersAbel Vesa1-97/+97
The arrays containing the mux selectors need to be of const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Make parents const pointer in mux wrappersAbel Vesa1-1/+2
The parents needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-02-21clk: imx: Make parent_names const pointer in composite-8mAbel Vesa2-2/+2
The parent_names needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24clk: imx: imx7ulp: use struct_size() in kzalloc()Gustavo A. R. Silva1-8/+8
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct foo { int stuff; void *entry[]; }; instance = kzalloc(sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL); Instead of leaving these open-coded and prone to type mistakes, we can now use the new struct_size() helper: instance = kzalloc(struct_size(instance, entry, count), GFP_KERNEL); This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-24clk: imx: Fix fractional clock set rate computationAbel Vesa1-2/+3
Before multiplying by PLL_FRAC_DENOM, the temp64 needs to be temp64 = rate * 2 - divfi * parent_rate * 8, instead of: temp64 = (rate * 2 - divfi) * parent_rate Fixes: 6209624b9a5c1e ("clk: imx: Add fractional PLL output clock") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-01-09clk: imx: fix potential NULL dereference in imx8qxp_lpcg_clk_probe()Wei Yongjun1-0/+2
platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Fixes: 1e3121bfe51a ("clk: imx: add imx8qxp lpcg driver") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28clk: vf610: fix refcount leak in vf610_clocks_init()Yangtao Li1-0/+1
The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 1f2c5fd5f048 ("ARM: imx: add VF610 clock support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28clk: imx7d: fix refcount leak in imx7d_clocks_init()Yangtao Li1-0/+1
The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 8f6d8094b215 ("ARM: imx: add imx7d clk tree support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28clk: imx6sx: fix refcount leak in imx6sx_clocks_init()Yangtao Li1-0/+1
The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: d55135689019 ("ARM: imx: add clock driver for imx6sx") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28clk: imx6q: fix refcount leak in imx6q_clocks_init()Yangtao Li1-0/+1
The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 2acd1b6f889c ("ARM: i.MX6: implement clocks using common clock framework") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-28clk: imx8qxp: make the name of clock ID genericAisheng Dong2-151/+151
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Let's make the name of clock ID generic to allow other SoCs to reuse the common part. This patch only changes the clock id name and file name, so no functional change. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14Merge branch 'clk-imx7ulp' into clk-nextStephen Boyd1-1/+30
* clk-imx7ulp: clk: imx: imx7ulp: add arm hsrun mode clocks support dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
2018-12-14clk: imx: imx7ulp: add arm hsrun mode clocks supportAnson Huang1-1/+30
i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode or HSRUN mode, it is controlled in SMC1 module. The RUN mode and HSRUN mode will use different clock source for ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN mode, so the control bits in SMC1 module can be abstracted as a HW clock mux, this patch adds HSRUN mode related clocks in SCG1 module and adds "arm" clock in SMC1 module to support RUN mode and HSRUN mode switch. Latest clock tree in RUN mode as below: firc 0 0 0 48000000 0 0 50000 firc_bus_clk 0 0 0 48000000 0 0 50000 hsrun_scs_sel 0 0 0 48000000 0 0 50000 hsrun_divcore 0 0 0 48000000 0 0 50000 sosc 3 3 3 24000000 0 0 50000 spll_pre_sel 1 1 1 24000000 0 0 50000 spll_pre_div 1 1 2 24000000 0 0 50000 spll 1 1 2 528000000 0 0 50000 spll_pfd0 1 1 1 500210526 0 0 50000 spll_pfd_sel 1 1 0 500210526 0 0 50000 spll_sel 1 1 0 500210526 0 0 50000 scs_sel 1 1 0 500210526 0 0 50000 divcore 1 1 0 500210526 0 0 50000 arm 1 1 0 500210526 0 0 50000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', ↵Stephen Boyd24-26/+3348
'clk-imx8qxp' and 'clk-imx8mq' into clk-next - NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM
2018-12-14clk: imx: add imx8qxp lpcg driverAisheng Dong3-1/+319
Add imx8qxp lpcg driver support Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: imx: add lpcg clock supportAisheng Dong3-1/+121
The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. And they're bedind the SCU clock. Cc: Stephen Boyd <sboyd@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: imx: add imx8qxp clk driverAisheng Dong3-0/+162
Add imx8qxp clk driver which is based on SCU firmware clock service. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Move the makefile rule higher in the file] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-14clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependantAbel Vesa2-0/+7
Remove the dependency between the i.MX8MQ CCM clock driver and the CONFIG_SOC_IMX8MQ and use CONFIG_CLK_IMX8MQ instead. CONFIG_CLK_IMX8MQ depends on ARCH_MXC && ARM64. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13clk: imx: add scu clock common partAisheng Dong4-0/+292
Add SCU clock common part which will be used by client clock drivers. SCU clocks are totally different from the legacy clocks (No much legacy things can be reused), it's using a firmware interface now based on SCU protocol. So a new configuration option CONFIG_MXC_CLK_SCU is added. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Mark ccm_ipc_handle static] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-13clk: imx: add configuration option for mmio clksAisheng Dong2-1/+6
The patch introduces CONFIG_MXC_CLK option for legacy MMIO clocks, this is required to compile legacy MMIO clock conditionally when adding SCU based clocks for MX8 platforms later. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: handle ENET PLL bypassLucas Stach1-6/+57
The ENET PLL is different from the other i.MX6 PLLs, as it has multiple outputs with different post-dividers, which are all bypassed if the single bypass bit is activated. The hardware setup looks something like this: _ refclk-o---PLL---o----DIV1-----| \ | | |M |----OUT1 o-----------------------|_/ | | _ | o----DIV2-----| \ | | |M |----OUT2 o-----------------------|_/ | | _ | `----DIV3-----| \ | |M |----OUT3 `-----------------------|_/ The bypass bit not only bypasses the PLL, but also the attached post-dividers. This would be reasonbly straight forward to model with a single output, or with different bypass bits for each output, but sadly the HW guys decided that it would be good to actuate all 3 muxes with a single bit. So the need to have the PLL bypassed for one of the outputs always affects 2 other (in our model) independent branches of the clock tree. This means the decision to bypass this PLL is a system wide design choice and should not be changed on-the-fly, so we can treat any bapass configuration as static. As such we can just register the post-dividiers with a ratio that reflects the bypass status, which allows us to bypass the PLL without breaking our abstraction model and with it DT stability. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: optionally get CCM inputs via standard clock handlesLucas Stach1-5/+17
When specifying external clock inputs to the CCM the current code requires the clocks to be in a "clocks" child node of the DT root. This is not really conformant with DT best practices. To avoid the need to deviate from those best practices, allow the clock inputs to be specified via standard clock handles. This is in line with how drivers of the later CCM driver revisions on newer i.MX SoCs handle this. As we can't retroactively change the DT binding, allow this as an option with a fallback to the old way of how this has been handled. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: reset exclusive gates on initLucas Stach1-1/+5
The exclusive gates may be set up in the wrong way by software running before the clock driver comes up. In that case the exclusive setup is locked in its initial state, as the complementary function can't be activated without disabling the initial setup first. To avoid this lock situation, reset the exclusive gates to the off state and allow the kernel to provide the proper setup. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Dong Aisheng <Aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6q: add DCICx clocks gateAnson Huang1-0/+2
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks gate in CCM_CCGR0 register, add them into clock tree for clock management. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx6sl: ensure MMDC CH0 handshake is bypassedAnson Huang1-0/+6
Same as other i.MX6 SoCs, ensure unused MMDC channel's handshake is bypassed, this is to make sure no request signal will be generated when periphe_clk_sel is changed or SRC warm reset is triggered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-10clk: imx: remove redundant initialization of ret to zeroColin Ian King1-1/+1
The initialization of ret is redundant as it is being re-assigned to the return value from the call to imx8m_clk_composite_compute_dividers. Clean this up by removing the initialization. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add imx7ulp clk driverA.s. Dong2-0/+221
i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks The clocking scheme provides clear separation between M4 domain and A7 domain. Except for a few clock sources shared between two domains, such as the System Oscillator clock, the Slow IRC (SIRC), and and the Fast IRC clock (FIRCLK), clock sources and clock management are separated and contained within each domain. M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. This driver only adds clock support in A7 domain. Note that most clocks required to be operated when gated, e.g. pll, pfd, pcc. And more special cases that scs/ddr/nic mux selecting different clock source requires that clock to be enabled first, then we need set CLK_OPS_PARENT_ENABLE flag for them properly. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: implement new clk_hw based APIsA.s. Dong2-0/+84
Clock providers are recommended to use the new struct clk_hw based API, so implement IMX clk_hw based provider helpers functions to the new approach. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: make mux parent strings constA.s. Dong3-9/+13
As the commit 2893c379461a ("clk: make strings in parent name arrays const"), let's make the parent strings const, otherwise we may meet the following warning when compiling: drivers/clk/imx/clk-imx7ulp.c: In function 'imx7ulp_clocks_init': drivers/clk/imx/clk-imx7ulp.c:73:35: warning: passing argument 5 of 'imx_clk_mux_flags' discards 'const' qualifier from pointer target type clks[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); ^ In file included from drivers/clk/imx/clk-imx7ulp.c:23:0: drivers/clk/imx/clk.h:200:27: note: expected 'const char **' but argument is of type 'const char * const*' ... Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add imx7ulp composite clk supportA.s. Dong3-0/+94
The imx composite clk is designed for Peripheral Clock Control (PCC) module observed in IMX ULP SoC series. NOTE pcc can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add pfdv2 supportA.s. Dong3-1/+208
The pfdv2 is designed for PLL Fractional Divide (PFD) observed in System Clock Generation (SCG) module in IMX ULP SoC series. e.g. i.MX7ULP. NOTE pfdv2 can only be operated when clk is gated. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add pllv4 supportA.s. Dong3-0/+188
pllv4 is designed for System Clock Generation (SCG) module observed in IMX ULP SoC series. e.g. i.MX7ULP. The SCG modules generates clock used to derive processor, system, peripheral bus and external memory interface clocks while this patch intends to support the PLL part. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Anson Huang <Anson.Huang@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: add gatable clock divider supportA.s. Dong3-0/+226
For dividers with zero indicating clock is disabled, instead of giving a warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set" in exist code, we'd like to introduce enable/disable function for it. e.g. 000b - Clock disabled 001b - Divide by 1 010b - Divide by 2 ... Set rate when the clk is disabled will cache the rate request and only when the clk is enabled will the driver actually program the hardware to have the requested divider value. Similarly, when the clk is disabled we'll write a 0 there, but when the clk is enabled we'll restore whatever rate (divider) was chosen last. It does mean that recalc rate will be sort of odd, because when the clk is off it will return 0, and when the clk is on it will return the right rate. So to make things work, we'll need to return the cached rate in recalc rate when the clk is off and read the hardware when the clk is on. NOTE for the default off divider, the recalc rate will still return 0 as there's still no proper preset rate. Enable such divider will give user a reminder error message. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> [sboyd@kernel.org: Include clk.h for sparse warnings] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-12-03clk: imx: Add SCCG PLL typeLucas Stach3-1/+267
The SCCG is a new PLL type introduced on i.MX8. The description of this SCCG clock can be found here: https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-28 07:06:12 +0000