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path: root/drivers/clk/hisilicon/clk.c
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2014-05-12clk: hisi: add hisi_clk_register_gateZhangfei Gao1-0/+28
Add hisi_clk_register_gate register clk gate table Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-05-12clk: hisi: use clk_register_mux_table in hisi_clk_register_muxZhangfei Gao1-5/+8
Platform hix5hd2 use mux table, so use clk_register_mux_table instead Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hisi: remove static variableHaojian Zhuang1-17/+47
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2014-03-19clk: hisi: assign missing clk to tableHaojian Zhuang1-0/+2
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-12-04clk: hisilicon: add common clock supportHaojian Zhuang1-0/+171
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is used to support the clock gate that enable/disable/status registers are seperated. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>