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2021-03-11media: aspeed: fix clock handling logicJae Hyun Yoo1-2/+2
Video engine uses eclk and vclk for its clock sources and its reset control is coupled with eclk so the current clock enabling sequence works like below. Enable eclk De-assert Video Engine reset 10ms delay Enable vclk It introduces improper reset on the Video Engine hardware and eventually the hardware generates unexpected DMA memory transfers that can corrupt memory region in random and sporadic patterns. This issue is observed very rarely on some specific AST2500 SoCs but it causes a critical kernel panic with making a various shape of signature so it's extremely hard to debug. Moreover, the issue is observed even when the video engine is not actively used because udevd turns on the video engine hardware for a short time to make a query in every boot. To fix this issue, this commit changes the clock handling logic to make the reset de-assertion triggered after enabling both eclk and vclk. Also, it adds clk_unprepare call for a case when probe fails. clk: ast2600: fix reset settings for eclk and vclk Video engine reset setting should be coupled with eclk to match it with the setting for previous Aspeed SoCs which is defined in clk-aspeed.c since all Aspeed SoCs are sharing a single video engine driver. Also, reset bit 6 is defined as 'Video Engine' reset in datasheet so it should be de-asserted when eclk is enabled. This commit fixes the setting. Fixes: d2b4387f3bdf ("media: platform: Add Aspeed Video Engine driver") Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Eddie James <eajames@linux.ibm.com> Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2021-02-11clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen1-10/+27
Starting from A2, the A-PLL calculation has changed. Use the existing formula for A0/A1 and the new formula for A2 onwards. Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Link: https://lore.kernel.org/r/20210119061715.6043-1-ryan_chen@aspeedtech.com Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11clk: AST2600: Add mux for EMMC clockEddie James1-8/+41
The EMMC clock can be derived from either the HPLL or the MPLL. Register a clock mux so that the rate is calculated correctly based upon the parent. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20200709195706.12741-2-eajames@linux.ibm.com Acked-by: Joel Stanley <joel@jms.id.au> Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27clk: ast2600: Fix AHB clock divider for A1Eddie James1-6/+25
The latest specs for the AST2600 A1 chip include some different bit definitions for calculating the AHB clock divider. Implement these in order to get the correct AHB clock value in Linux. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lkml.kernel.org/r/20200408203616.4031-1-eajames@linux.ibm.com Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-01Merge tag 'clk-for-linus' of ↵Linus Torvalds1-3/+46
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This merge window we have one small clk provider API in the core framework and then a bunch of driver updates and a handful of new drivers. In terms of diffstat the Qualcomm and Amlogic drivers are high up there because of all the clk data introcued by new drivers. The Nvidia Tegra driver had a lot of work done this cycle too to support suspend/resume and memory controllers. And the OMAP clk driver got proper clk and reset handling in place. Rounding out the patches are various updates to remove unused data, mark things static, correct incorrect data in drivers, etc. All the little things that improve drivers and maintain code health. I will point out that there's a patch in here for the GPIO clk driver, that almost nobody uses, which changes behavior and causes clk_set_rate() to try to change the GPIO gate clk's parent. Other than that things are fairly well SoC specific here. Core: - Add a clk provider API to get current parent index - Plug a memory leak in clk_unregister() path New Drivers: - CGU in Ingenix X1000 - Bitmain BM1880 clks - Qualcomm MSM8998 GPU clk controllers - Qualcomm SC7180 GCC and RPMH clk controllers - Qualcomm QCS404 Q6SSTOP clk controllers - Add support for the Renesas R-Car M3-W+ (r8a77961) SoC - Add support for the Renesas RZ/G2N (r8a774b1) SoC - Add Tegra20/30 External Memory Clock (EMC) support Updates: - Make gpio gate clks propagate rate setting up to parent - Prepare Armada 3700 for suspend to RAM by moving PCIe suspend/resume priority - Drop unused variables, enums, etc. in various clk drivers - Convert various drivers to use devm_platform_ioremap_resource() - Use struct_size() some more in various clk drivers - Improve Rockchip px30 clk tree - Add suspend/resume support to Tegra210 clk driver - Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP - Allwinner DT exports and H6 clk tree fixes - Proper clk and reset handling for OMAP SoCs - Revamped TI divider clk to clamp max divider - Make 1443X/1416X PLL clock structure common for reusing among i.MX8 SoCs - Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used - Add VIDEO2_PLL clock for imx8mq - Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs - Add sm1 support in the Amlogic audio clock controller - Switch some clocks on R-Car Gen2/3 to .determine_rate() - Remove Renesas R-Car Gen2 legacy DT clock support - Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3 - Improve Renesas R-Car Gen3 SD clock handling - Add rate table for Samsung exynos542x GPU and VPLL clks - Fix potential CPU performance degradation after system suspend/resume cycle on exynos542x SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (160 commits) clk: aspeed: Add RMII RCLK gates for both AST2500 MACs MAINTAINERS: Add entry for BM1880 SoC clock driver clk: Add common clock driver for BM1880 SoC dt-bindings: clock: Add devicetree binding for BM1880 SoC clk: Add clk_hw_unregister_composite helper function definition clk: Zero init clk_init_data in helpers clk: ingenic: Allow drivers to be built with COMPILE_TEST MAINTAINERS: Update section for Ux500 clock drivers clk: mark clk_disable_unused() as __init clk: Fix memory leak in clk_unregister() clk: Ingenic: Add CGU driver for X1000. dt-bindings: clock: Add X1000 bindings. clk: tegra: Use match_string() helper to simplify the code clk: pxa: fix one of the pxa RTC clocks clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle() clk: armada-xp: remove unused code clk: tegra: Fix build error without CONFIG_PM_SLEEP clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP clk: tegra: Optimize PLLX restore on Tegra20/30 clk: tegra: Add suspend and resume support on Tegra210 ...
2019-11-27Merge branches 'clk-ti', 'clk-allwinner', 'clk-qcom', 'clk-sa' and ↵Stephen Boyd1-1/+46
'clk-aspeed' into clk-next - Qualcomm MSM8998 GPU clk controllers - Qualcomm SC7180 GCC and RPMH clk controllers - Qualcomm QCS404 Q6SSTOP clk controllers - Use struct_size() some more in various clk drivers * clk-ti: clk/ti/adpll: allocate room for terminating null ARM: dts: omap3: fix DPLL4 M4 divider max value clk: ti: divider: convert to use min,max,mask instead of width clk: ti: divider: cleanup ti_clk_parse_divider_data API clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table clk: ti: am43xx: drop idlest polling from gfx clock clk: ti: am33xx: drop idlest polling from gfx clock clk: ti: am33xx: drop idlest polling from pruss clkctrl clock clk: ti: am43xx: drop idlest polling from pruss clkctrl clock clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocks clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocks clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocks clk: ti: omap5: add IVA subsystem clkctrl data dt-bindings: clk: add omap5 iva clkctrl definitions clk: ti: clkctrl: add new exported API for checking standby info clk: ti: clkctrl: convert to use bit helper macros instead of bitops clk: ti: clkctrl: fix setting up clkctrl clocks * clk-allwinner: clk: sunxi-ng: h3: Export MBUS clock clk: sunxi-ng: h6: Allow GPU to change parent rate clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL * clk-qcom: clk: qcom: rpmh: Reuse sdm845 clks for sm8150 clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver clk: qcom: Allow constant ratio freq tables for rcg clk: qcom: smd: Add missing pnoc clock clk: qcom: Enumerate clocks and reset needed to boot the 8998 modem clk: qcom: clk-rpmh: Add support for RPMHCC for SC7180 dt-bindings: clock: Introduce RPMHCC bindings for SC7180 dt-bindings: clock: Add YAML schemas for the QCOM RPMHCC clock bindings clk: qcom: Add Global Clock controller (GCC) driver for SC7180 dt-bindings: clock: Add sc7180 GCC clock binding dt-bindings: clock: Add YAML schemas for the QCOM GCC clock bindings clk: qcom: common: Return NULL from clk_hw OF provider clk: qcom: rcg: update the DFS macro for RCG clk: qcom: remove unneeded semicolon clk: qcom: Add Q6SSTOP clock controller for QCS404 dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings * clk-sa: drivers/clk: convert VL struct to struct_size * clk-aspeed: clk: aspeed: Add RMII RCLK gates for both AST2500 MACs clk: ast2600: Add RMII RCLK gates for all four MACs dt-bindings: clock: Add AST2600 RMII RCLK gate definitions dt-bindings: clock: Add AST2500 RMII RCLK definitions
2019-11-08clk: ast2600: Add RMII RCLK gates for all four MACsAndrew Jeffery1-1/+46
RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a single gate for each MAC. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-28clk: ast2600: Fix enabling of clocksJoel Stanley1-3/+4
The struct clk_ops enable callback for the aspeed gates mixes up the set to clear and write to set registers. Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC") Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20191016131319.31318-1-joel@jms.id.au Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16clk: ast2600: remove unused variable 'eclk_parent_names'YueHaibing1-2/+0
drivers/clk/clk-ast2600.c:119:27: warning: eclk_parent_names defined but not used [-Wunused-const-variable=] It is never used, so can be removed. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20191015115117.23504-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: Add support for AST2600 SoCJoel Stanley1-0/+704
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks than the previous iterations, so support is broken out into it's own driver. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au [sboyd@kernel.org: Mark arrays const] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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