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path: root/drivers/clk/bcm
AgeCommit message (Expand)AuthorFilesLines
2016-09-14clk-kona-setup: Use kmalloc_array() in parent_process()Markus Elfring1-2/+2
2016-09-07clk: bcm2835: Skip PLLC clocks when deciding on a new clock parentEric Anholt1-0/+23
2016-09-07clk: bcm2835: Mark the CM SDRAM clock's parent as criticalEric Anholt1-0/+25
2016-09-07clk: bcm2835: Mark GPIO clocks enabled at boot as criticalEric Anholt1-1/+9
2016-09-07clk: bcm2835: Mark the VPU clock as criticalEric Anholt1-1/+4
2016-08-24clk: bcm: kona: Migrate to clk_hw based registration and OF APIsStephen Boyd3-51/+41
2016-06-30clk: bcm: iproc: Migrate to clk_hw based registration and OF APIsStephen Boyd3-35/+33
2016-06-20clk: iproc: fix missing include of clk-iproc.hBen Dooks1-0/+2
2016-05-06clk: bcm/kona: Do not use sizeof on pointer typeVaishali Thakkar1-1/+2
2016-04-19clk: bcm2835: Fix PLL poweronEric Anholt1-0/+4
2016-04-19clk: bcm2835: Fix compiler warnings on 64-bit buildsEric Anholt1-4/+4
2016-03-17clk: bcm2835: add missing osc and per clocksMartin Sperl1-0/+90
2016-03-17clk: bcm2835: add missing PLL clock dividersMartin Sperl1-0/+32
2016-03-17clk: bcm2835: enable management of PCM clockMartin Sperl1-0/+7
2016-03-17clk: bcm2835: reorganize bcm2835_clock_array assignmentMartin Sperl1-459/+393
2016-03-17clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driverMartin Sperl1-73/+94
2016-03-17clk: bcm2835: expose raw clock-registers via debugfsMartin Sperl1-0/+101
2016-03-17clk: bcm2835: clean up coding style issuesMartin Sperl1-6/+2
2016-03-17clk: bcm2835: correctly enable fractional clock supportMartin Sperl1-6/+39
2016-03-17clk: bcm2835: divider value has to be 1 or moreMartin Sperl1-2/+3
2016-03-17clk: bcm2835: add locking to pll*_on/off methodsMartin Sperl1-0/+4
2016-03-17clk: bcm2835: pll_off should only update CM_PLL_ANARSTMartin Sperl1-2/+8
2016-03-15clk: bcm2835: fix check of error code returned by devm_ioremap_resource()Vladimir Zapolskiy1-2/+2
2016-03-02clk: bcm: Remove CLK_IS_ROOTStephen Boyd1-6/+3
2016-02-25clk: bcm2835: added missing clock register definitionsMartin Sperl1-0/+13
2016-02-16Merge branch 'clk-bcm2835' into clk-nextMichael Turquette1-16/+9
2016-02-16clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()Eric Anholt1-11/+2
2016-02-16clk: bcm2835: Fix setting of PLL divider clock ratesEric Anholt1-5/+7
2016-01-29clk: iproc: Remove __init from headerRay Jui1-11/+11
2016-01-29clk: iproc: Add support for Cygnus audio clocksSimran Rai3-5/+116
2015-12-24Merge branch 'clk-bcm2835' into clk-nextMichael Turquette1-54/+101
2015-12-24clk: bcm2835: Add PWM clock supportRemi Pommarel1-0/+13
2015-12-24clk: bcm2835: Support for clock parent selectionRemi Pommarel1-45/+77
2015-12-24clk: bcm2835: add a round up ability to the clock divisorRemi Pommarel1-10/+12
2015-12-22Merge branch 'clk-bcm2835' into clk-nextMichael Turquette2-0/+86
2015-12-22clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.Eric Anholt2-0/+86
2015-11-20clk: bcm: Add BCM63138 clock supportFlorian Fainelli3-0/+33
2015-10-21Merge branch 'clk-iproc' into clk-nextStephen Boyd7-157/+637
2015-10-21clk: ns2: add clock support for Broadcom Northstar 2 SoCJon Mason2-0/+289
2015-10-21clk: iproc: Separate status and control variablesJon Mason2-40/+62
2015-10-21clk: iproc: Split off dig_filterJon Mason4-17/+38
2015-10-21clk: iproc: Add PLL base write functionJon Mason1-47/+33
2015-10-21clk: nsp: add clock support for Broadcom Northstar Plus SoCJon Mason2-0/+137
2015-10-21clk: iproc: Add PWRCTRL supportJon Mason2-17/+44
2015-10-21clk: cygnus: Convert all macros to all capsJon Mason1-73/+73
2015-10-21ARM: cygnus: fix link failures when CONFIG_COMMON_CLK_IPROC is disabledArnd Bergmann1-3/+1
2015-10-21clk: iproc: Fix PLL output frequency calculationSimran Rai1-8/+5
2015-10-16clk: Allow drivers to build if COMPILE_TEST is enabledJavier Martinez Canillas1-2/+2
2015-10-12clk: bcm2835: Add support for programming the audio domain clocksEric Anholt1-1/+1521
2015-10-01clk: bcm2835: Move under bcm/ with other Broadcom SoC clk drivers.Eric Anholt2-0/+56