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2022-05-19Merge tag 'mhi-for-v5.19' of ↵Greg Kroah-Hartman6-63/+223
git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi into char-work-next Manivannan writes: MHI changes for v5.19 MHI Host -------- Support for new modems: - Foxconn Cinterion MV32-WA/MV32-WB based on SDX62/SDX65 - Telit FN980 v1 based on SDX55 - Telit FN990 based on SDX65 - Foxconn T99W373/T99W368 based on SDX62/SDX65 Core changes: - During the recycle of event ring elements, compute the ctxt_wp based on the local cached value instead of reading from shared memory. This is to prevent the possible corruption of the ctxt_wp as some of the endpoint devices could modify the value in shared memory. - Add sysfs support for resetting the endpoint based on the MHI spec. The MHI spec allows the host to hard reset the device in the case of an unrecoverable error and all other reset mechanisms have failed. - During MHI shutdown, wait for the endpoint device to enter the ready state post reset before proceeding. This is to avoid a possible race where host would remove the interrupt handler and device will send ready state interrupt, resulting in IOMMU fault. - Bail out updating the MHI register if the read has failed during read/modify/write. - Use mhi_write_reg() instead of mhi_write_reg_field() for writing the whole register fields in mhi_init_mmio(). MAINTAINERS change: - Since Qualcomm has moved the email domain for its employess from codeaurora domain to quicinc, update the same for Hemant. * tag 'mhi-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi: (29 commits) bus: mhi: host: Add support for Foxconn T99W373 and T99W368 bus: mhi: host: pci_generic: add Telit FN990 bus: mhi: host: pci_generic: add Telit FN980 v1 hardware revision bus: mhi: host: Add support for Cinterion MV32-WA/MV32-WB bus: mhi: host: Optimize and update MMIO register write method bus: mhi: host: Bail on writing register fields if read fails bus: mhi: host: Wait for ready state after reset bus: mhi: host: Add soc_reset sysfs bus: mhi: host: pci_generic: Sort mhi_pci_id_table based on the PID bus: mhi: host: Use cached values for calculating the shared write pointer MAINTAINERS: Update Hemant's email id bus: mhi: ep: Add uevent support for module autoloading bus: mhi: ep: Add support for suspending and resuming channels bus: mhi: ep: Add support for queueing SKBs to the host bus: mhi: ep: Add support for processing channel rings bus: mhi: ep: Add support for reading from the host bus: mhi: ep: Add support for processing command rings bus: mhi: ep: Add support for handling SYS_ERR condition bus: mhi: ep: Add support for handling MHI_RESET bus: mhi: ep: Add support for powering down the MHI endpoint stack ...
2022-05-10bus: mhi: host: Add support for Foxconn T99W373 and T99W368Slark Xiao1-0/+15
Product's enumeration align with previous Foxconn SDX55, so T99W373(SDX62)/T99W368(SDX65) would use the same config as Foxconn SDX55. Remove fw and edl for this new commit. Signed-off-by: Slark Xiao <slark_xiao@163.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Link: https://lore.kernel.org/r/20220503024349.4486-1-slark_xiao@163.com Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-05-10bus: mhi: host: pci_generic: add Telit FN990Daniele Palmas1-0/+41
Add Telit FN990: 01:00.0 Unassigned class [ff00]: Qualcomm Device 0308 Subsystem: Device 1c5d:2010 Signed-off-by: Daniele Palmas <dnlplm@gmail.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20220502112036.443618-1-dnlplm@gmail.com [mani: Added "host" to the subject] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-05-10bus: mhi: host: pci_generic: add Telit FN980 v1 hardware revisionDaniele Palmas1-0/+38
Add Telit FN980 v1 hardware revision: 01:00.0 Unassigned class [ff00]: Qualcomm Device [17cb:0306] Subsystem: Device [1c5d:2000] Signed-off-by: Daniele Palmas <dnlplm@gmail.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20220427072648.17635-1-dnlplm@gmail.com [mani: Added "host" to the subject] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-05-09bus: mhi: replace snprintf with sysfs_emitWan Jiabing1-4/+3
Fix following coccicheck warning: ./drivers/bus/mhi/host/init.c:89:8-16: WARNING: use scnprintf or sprintf Use sysfs_emit and sysfs_emit_at instead of snprintf. Reviewed-by: Kees Cook <keescook@chromium.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Link: https://lore.kernel.org/r/20220426125902.681258-1-wanjiabing@vivo.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-04-23bus: mhi: host: Add support for Cinterion MV32-WA/MV32-WBSlark Xiao1-8/+22
MV32-WA is designed based on Qualcomm SDX62, and MV32-WB is designed based on QUalcomm SDX65. Both products' enumeration would align with previous product MV31-W.So we merge MV31 and MV32 to MV3X for some common settings. Signed-off-by: Slark Xiao <slark_xiao@163.com> Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://lore.kernel.org/r/20220421092141.3984-1-slark_xiao@163.com [mani: removed the fixes tag that's not needed] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-23bus: mhi: host: Optimize and update MMIO register write methodBhaumik Bhatt1-31/+31
As of now, MMIO writes done after ready state transition use the mhi_write_reg_field() API even though the whole register is being written in most cases. Optimize this process by using mhi_write_reg() API instead for those writes and use the mhi_write_reg_field() API for MHI config registers only. Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1650304226-11080-3-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-23bus: mhi: host: Bail on writing register fields if read failsBhaumik Bhatt5-21/+54
Helper API to write register fields relies on successful reads of the register/address prior to the write. Bail out if a failure is seen when reading the register before the actual write is performed. Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org> Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1650304226-11080-2-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-23bus: mhi: host: Wait for ready state after resetJeffrey Hugo1-0/+9
After the device has signaled the end of reset by clearing the reset bit, it will automatically reinit MHI and the internal device structures. Once That is done, the device will signal it has entered the ready state. Signaling the ready state involves sending an interrupt (MSI) to the host which might cause IOMMU faults if it occurs at the wrong time. If the controller is being powered down, and possibly removed, then the reset flow would only wait for the end of reset. At which point, the host and device would start a race. The host may complete its reset work, and remove the interrupt handler, which would cause the interrupt to be disabled in the IOMMU. If that occurs before the device signals the ready state, then the IOMMU will fault since it blocked an interrupt. While harmless, the fault would appear like a serious issue has occurred so let's silence it by making sure the device hits the ready state before the host completes its reset processing. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Hemant Kumar <quic_hemantk@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1650302562-30964-1-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-23bus: mhi: host: Add soc_reset sysfsJeffrey Hugo1-0/+14
The MHI bus supports a standardized hardware reset, which is known as the "SoC Reset". This reset is similar to the reset sysfs for PCI devices - a hardware mechanism to reset the state back to square one. The MHI SoC Reset is described in the spec as a reset of last resort. If some unrecoverable error has occurred where other resets have failed, SoC Reset is the "big hammer" that ungracefully resets the device. This is effectivly the same as yanking the power on the device, and reapplying it. However, depending on the nature of the particular issue, the underlying transport link may remain active and configured. If the link remains up, the device will flag a MHI system error early in the boot process after the reset is executed, which allows the MHI bus to process a fatal error event, and clean up appropiately. While the SoC Reset is generally intended as a means of recovery when all else has failed, it can be useful in non-error scenarios. For example, if the device loads firmware from the host filesystem, the device may need to be fully rebooted inorder to pick up the new firmware. In this scenario, the system administrator may use the soc_reset sysfs to cause the device to pick up the new firmware that the admin placed on the filesystem. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Bhaumik Bhatt <quic_bbhatt@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1650302327-30439-1-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-23bus: mhi: host: pci_generic: Sort mhi_pci_id_table based on the PIDManivannan Sadhasivam1-4/+5
Sorting this way helps in identifying the products of vendors. There is no sorting required for VID and the new VID should be added as the last entry. Let's also add a note clarifying this. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Daniele Palmas <dnlplm@gmail.com> Link: https://lore.kernel.org/r/20220411133428.42165-1-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-23bus: mhi: host: Use cached values for calculating the shared write pointerJeffrey Hugo1-7/+2
mhi_recycle_ev_ring() computes the shared write pointer for the ring (ctxt_wp) using a read/modify/write pattern where the ctxt_wp value in the shared memory is read, incremented, and written back. There are no checks on the read value, it is assumed that it is kept in sync with the locally cached value. Per the MHI spec, this is correct. The device should only read ctxt_wp, never write it. However, there are devices in the wild that violate the spec, and can update the ctxt_wp in a specific scenario. This can cause corruption, and violate the above assumption that the ctxt_wp is in sync with the cached value. This can occur when the device has loaded firmware from the host, and is transitioning from the SBL EE to the AMSS EE. As part of shutting down SBL, the SBL flushes it's local MHI context to the shared memory since the local context will not persist across an EE change. In the case of the event ring, SBL will flush its entire context, not just the parts that it is allowed to update. This means SBL will write to ctxt_wp, and possibly corrupt it. An example: Host Device ---- --- Update ctxt_wp to 0x1f0 SBL observes 0x1f0 Update ctxt_wp to 0x0 Starts transition to AMSS EE Context flush, writes 0x1f0 to ctxt_wp Update ctxt_wp to 0x200 Update ctxt_wp to 0x210 AMSS observes 0x210 0x210 exceeds ring size AMSS signals syserr The reason the ctxt_wp goes off the end of the ring is that the rollover check is only performed on the cached wp, which is out of sync with ctxt_wp. Since the host is the authority of the value of ctxt_wp per the MHI spec, we can fix this issue by not reading ctxt_wp from the shared memory, and instead compute it based on the cached value. If SBL corrupts ctxt_wp, the host won't observe it, and will correct the value at some point later. Signed-off-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Hemant Kumar <quic_hemantk@quicinc.com> Reviewed-by: Bhaumik Bhatt <quic_bbhatt@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1649868113-18826-1-git-send-email-quic_jhugo@quicinc.com [mani: used the quicinc domain for Hemant and Bhaumik] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-13bus: mhi: host: pci_generic: Flush recovery worker during freezeManivannan Sadhasivam1-0/+1
It is possible that the recovery work might be running while the freeze gets executed (during hibernation etc.,). Currently, we don't powerdown the stack if it is not up but if the recovery work completes after freeze, then the device will be up afterwards. This will not be a sane situation. So let's flush the recovery worker before trying to powerdown the device. Cc: stable@vger.kernel.org Fixes: 5f0c2ee1fe8d ("bus: mhi: pci-generic: Fix hibernation") Reported-by: Bhaumik Vasav Bhatt <quic_bbhatt@quicinc.com> Reviewed-by: Bhaumik Vasav Bhatt <quic_bbhatt@quicinc.com> Link: https://lore.kernel.org/r/20220408150039.17297-1-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-04-13bus: mhi: host: pci_generic: Add missing poweroff() PM callbackManivannan Sadhasivam1-0/+1
During hibernation process, once thaw() stage completes, the MHI endpoint devices will be in M0 state post recovery. After that, the devices will be powered down so that the system can enter the target sleep state. During this stage, the PCI core will put the devices in D3hot. But this transition is allowed by the MHI spec. The devices can only enter D3hot when it is in M3 state. So for fixing this issue, let's add the poweroff() callback that will get executed before putting the system in target sleep state during hibernation. This callback will power down the device properly so that it could be restored during restore() or thaw() stage. Cc: stable@vger.kernel.org Fixes: 5f0c2ee1fe8d ("bus: mhi: pci-generic: Fix hibernation") Reported-by: Hemant Kumar <quic_hemantk@quicinc.com> Suggested-by: Hemant Kumar <quic_hemantk@quicinc.com> Link: https://lore.kernel.org/r/20220405125907.5644-1-manivannan.sadhasivam@linaro.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-03-18bus: mhi: Make mhi_state_str[] array static inline and move to common.hManivannan Sadhasivam5-27/+15
mhi_state_str[] array could be used by MHI endpoint stack also. So let's make the array as "static inline function" and move it inside the "common.h" header so that the endpoint stack could also make use of it. Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-11-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-18bus: mhi: Move common MHI definitions out of host directoryManivannan Sadhasivam1-263/+1
Move the common MHI definitions in host "internal.h" to "common.h" so that the endpoint code can make use of them. This also avoids duplicating the definitions in the endpoint stack. Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-10-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-18bus: mhi: host: Rename "struct mhi_tre" to "struct mhi_ring_element"Manivannan Sadhasivam3-14/+14
Structure "struct mhi_tre" is representing a generic MHI ring element and not specifically a Transfer Ring Element (TRE). Fix the naming. Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-9-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-18bus: mhi: Cleanup the register definitions used in headersManivannan Sadhasivam1-214/+199
Cleanup includes: 1. Using the GENMASK macro for masks 2. Removing brackets for single values 3. Using lowercase for hex values 4. Using two digits for hex values where applicable 5. Aligning the defines on same column Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-8-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-18bus: mhi: Use bitfield operations for handling DWORDs of ring elementsManivannan Sadhasivam1-25/+33
Instead of using the hardcoded bits in DWORD definitions, let's use the bitfield operations to make it more clear how the DWORDs are structured. Suggested-by: Alex Elder <elder@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-7-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-18bus: mhi: Use bitfield operations for register read and writeManivannan Sadhasivam6-170/+76
Functions like mhi_read_reg_field(), mhi_poll_reg_field() and mhi_write_reg_field() could be modified to not depend on the shift value passed as an argument. Instead, the bitfield operation could be used to extract the shift value from the mask itself. This eliminates the need to define _SHIFT (and _SHFT) macros and simplifies the code a bit. For shift values those cannot be determined during build time, "__ffs()" helper is used find the shift value during runtime. While at it, let's also get rid of 32-bit masks like CHDBOFF_CHDBOFF_MASK by doing the full 32-bit register read. Suggested-by: Alex Elder <elder@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-6-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-03-18bus: mhi: Move host MHI code to "host" directoryManivannan Sadhasivam9-0/+7189
In preparation of the endpoint MHI support, let's move the host MHI code to its own "host" directory and adjust the toplevel MHI Kconfig & Makefile. While at it, let's also move the "pci_generic" driver to "host" directory as it is a host MHI controller driver. Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220301160308.107452-5-manivannan.sadhasivam@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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