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2017-06-02ahci: qoriq: add ls1088a platforms supportYuantian Tang1-0/+14
Ls1088a is new introduced arm-based soc with sata support with following features: * Complies with the serial ATA 3.0 specification and the AHCI 1.3.1 specification * Contains a high-speed descriptor-based DMA controller * Supports the following: * Speeds of 1.5 Gb/s (first-generation SATA), 3 Gb/s (second-generation SATA), and 6 Gb/s (third-generation SATA) * FIS-based switching * Native command queuing (NCQ) commands * Port multiplier operation * Asynchronous notification * SATA Vendor BIST mode Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-03-09ahci: qoriq: correct the sata ecc setting errorYuantian Tang1-2/+4
Sata ecc is controlled by only 1 bit which is 24bit in big-endian in ecc register. So only setting 24bit to disable sata ecc prevents other bits from being overwritten in ecc register. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-01-20ahci: qoriq: added ls2088a platforms supportTang Yuantian1-0/+9
Ls2088a is new introduced arm-based soc with sata support with following features: 1. Complies with the serial ATA 3.0 specification and the AHCI 1.3.1 specification 2. Contains a high-speed descriptor-based DMA controller 3. Supports the following: a. Speeds of 1.5 Gb/s (first-generation SATA), 3 Gb/s (second-generation SATA), and 6 Gb/s (third-generation SATA) b. FIS-based switching c. Native command queuing (NCQ) commands d. Port multiplier operation e. Asynchronous notification f. SATA BIST mode Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-01-20ahci: qoriq: report error when ecc register address is missing in dtsTang Yuantian1-2/+9
For ls1021a, and armv8 chasis 2 socs, sata ecc must be disabled. If ecc register is not found in sata node in dts, report error. This is a chip erratum described as bellow: The Read DMA operations get early termination indication from the controller. This issue is observed as CRC error in the status registers. The issue is due to address collision at address 0 in the dual port memory. The read is a dummy read to flush out the header, but due to collision the controller logs the mbit error reported by the ECC check logic. This results in the early termination of the Read DMA operation by the controller. The issue happens to all the interface speeds(GEN1/2/3) for all the products. Workaround: Disable ECC feature on those platforms. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2017-01-20ahci: qoriq: added a condition to enable dma coherenceTang Yuantian1-4/+11
Enable DMA coherence in SATA controller on condition that dma-coherent property exists in sata node in DTS. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-10-19ahci: qoriq: added ls1046a platform supportTang Yuantian1-3/+13
Ls1046a is a new introduced soc which supports ATA3.0. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-09-30ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC"Tang Yuantian1-7/+1
This reverts commit 640847298e2b7f19 ("ahci: qoriq: Disable NCQ on ls2080a SoC") The erratum has been fixed in ls2080a v2.0 and later soc. In reality, customer will not get any ls2080a v1.0 soc. Neither apply to any products. So reverting this commit won't create any side effect. Blacklisting v2.0 could also be a option, but that needs to check the soc version which is not suitable in the driver. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-08-10ahci: qoriq: enable snoopable sata read and writeTang Yuantian1-0/+6
By default the SATA IP on the qoriq SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2016-08-10ahci: qoriq: adjust sata parameterTang Yuantian1-6/+0
The default values for Port Phy2Cfg register and Port Phy3Cfg register are better, no need to overwrite them. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-12-16ahci: qoriq: Adjust the default register values on ls1021aTang Yuantian1-10/+14
Updated the registers' values to enhance SATA performance and reliability on ls1021a soc. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-12-16ahci: qoriq: Update the default Rx watermark valueTang Yuantian1-1/+2
The PTC[RXWM] sets the watermark value for Rx FIFO. The default value 0x20 might be insufficient for some hard drives. If the watermark value is too small, a single-cycle overflow may occur and is reported as a CRC or internal error in the PxSERR register. Updated the value to 0x29 according to the validation test. All LS platforms are affected. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-12-16ahci: qoriq: Adjust the default register values on ls1043aTang Yuantian1-0/+8
Updated the registers' values to enhance SATA performance and reliability. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-10-31ahci: qoriq: Disable NCQ on ls2080a SoCTang Yuantian1-1/+7
NCQ feature can't be used due to the erratum A-008473. This patch disables NCQ as a workaround. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-10-31ahci: qoriq: Rename LS2085A SoC support code to LS2080ATang Yuantian1-3/+3
Freescale is renaming the LS2085A SoC to LS2080A. This patch addresses the same. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-10-15ahci: qoriq: Fix a compiling warningArnd Bergmann1-2/+3
kbuild test robot reports the warnings: drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset': >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used >> uninitialized in this function [-Wuninitialized] drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used >> uninitialized in this function [-Wuninitialized] drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here This patch fixed it by introducing a local variable. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Tejun Heo <tj@kernel.org>
2015-09-08ahci: added a new driver for supporting Freescale AHCI sataTang Yuantian1-0/+272
Currently Freescale QorIQ series SATA is supported by ahci_platform driver. Some SoC specific settings have been put in uboot. So whether SATA works or not heavily depends on uboot. This patch will add a new driver to support QorIQ sata which removes the dependency on any other boot loader. Freescale QorIQ series sata, like ls1021a ls2085a ls1043a, is compatible with serial ATA 3.0 and AHCI 1.3 specification. Signed-off-by: Yuantian Tang <Yuantian.Tang@freescale.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
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