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2010-10-27MN10300: ASB2364: Add support for SMSC911X and SMC911XAkira Takeuchi5-0/+233
Add support for SMSC911X and SMC911X for the ASB2364 unit. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com> cc: steve.glendinning@smsc.com cc: netdev@vger.kernel.org
2010-10-27MN10300: ASB2364: Handle the IRQ multiplexer in the FPGADavid Howells7-19/+166
Handle the IRQ multiplexer in the FPGA by implementing a cascade interrupt driver for it. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Generic time supportMark Salter12-115/+401
Implement generic time support for MN10300. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Specify an ELF HWCAP flag for MN10300 Atomic Operations Unit supportMark Salter1-0/+10
Use an ELF HWCAP flag to indicate to the process that the CPU provides LL/SC equivalent atomic operations unit support in addition to BSET/BCLR. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Map userspace atomic op regs as a vmalloc pageMark Salter2-0/+24
The AM34 processor has an atomic operation that's the equivalent of LL/SC on other architectures. However, rather than being done through a pair of instructions, it's driven by writing to a pair of memory-mapped CPU control registers. One set of these registers (AARU/ADRU/ASRU) is available for use by userspace, but for userspace to access them a PTE must be set up to cover the region. This is done by dedicating the first vmalloc region page to this purpose, setting the permissions on its PTE such that userspace can access the page. glibc is hardcoded to expect the registers to be there. The way atomic ops are done through these registers is straightforward: (1) Write the address of the word you wish to access into AARU. This causes the CPU to go and fetch that word and load it into ADRU. The status bits are also cleared in ASRU. (2) The current data value is read from the ADRU register and modified. (3) To alter the data in RAM, the revised data is written back to the ADRU register, which causes the CPU to attempt to write it back. (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch), ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then must be checked to confirm that the operation wasn't aborted. If any of the watches have been set to true, the operation was aborted. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: And Panasonic AM34 subarch and implement SMPAkira Takeuchi79-481/+4494
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Delete idle_timestamp from irq_cpustat_tAkira Takeuchi2-3/+0
Delete idle_timestamp from irq_cpustat_t as it's an unread relic. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make various interrupt priority settings configurableAkira Takeuchi2-6/+76
Make the settings of interrupt priorities used by various services configurable at run time. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Optimise do_csum()Akira Takeuchi1-27/+22
Optimise do_csum() to gang up the loads so they're less likely to get interruptions between. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Implement atomic ops using atomic ops unitMark Salter2-47/+351
Implement atomic ops using the atomic ops unit available in the AM34 CPU. This allows the equivalent of the LL/SC instructions to be found on other CPUs. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make the FPU operate in non-lazy mode under SMPAkira Takeuchi14-248/+440
Make the FPU operate in non-lazy mode under SMP so that when the process that is currently using the FPU migrates to a different CPU, we don't have to ping its previous CPU to flush the FPU context. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: SMP TLB flushingAkira Takeuchi4-29/+290
Implement global TLB flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB controlAkira Takeuchi3-47/+65
Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control as the bits are a more suitable layout. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make the use of PIDR to mark TLB entries controllableAkira Takeuchi4-62/+84
Make controllable the use of the PIDR register to mark TLB entries as belonging to particular processes. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Rename __flush_tlb*() to local_flush_tlb*()David Howells6-28/+42
Rename __flush_tlb*() to local_flush_tlb*() as it's more appropriate, and ready to differentiate local from global TLB flushes when SMP is introduced. Whilst we're at it, get rid of __flush_tlb_global() and make local_flush_tlb_page() take an mm_struct pointer rather than VMA pointer. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: AM34 erratum requires MMUCTR read and write on exception entryAkira Takeuchi3-6/+37
An AM34 erratum requires MMUCTR read and write on entry to certain exceptions, prior to EPSW.NMID being cleared to allow NMIs to happen. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Make the boot wrapper able to use writeback cachingAkira Takeuchi1-1/+48
Make the boot wrapper able to use writeback caching, including flushing the cache before jumping to the main kernel. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Cache: Implement SMP global cache flushingAkira Takeuchi9-15/+535
Implement SMP global cache flushing for MN10300. This will be used by the AM34 which is SMP capable. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Allow some cacheflushes to be avoided if cache snooping is availableDavid Howells9-96/+309
The AM34 core is able to do cache snooping, and so can skip some of the cache flushing. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: AM34: Add cacheflushing by using the AM34 purge registersAkira Takeuchi4-1/+678
The AM34 CPU core provides an automated way of purging the cache rather than manually iterating over all the tags in the cache. Make it possible to use these. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: SMP: Differentiate local cache flushingAkira Takeuchi4-112/+289
Differentiate local cache flushing from global cache flushing so that they can be done differently on SMP systems. Rename the cache functions from: mn10300_[id]cache_*() to: mn10300_[id]_localcache_*() and on a UP system, assign the global labels to the local labels. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Cacheflush functions should take unsigned long addressesAkira Takeuchi2-15/+15
The functions that perform cache flushing should take addresses of unsigned long type, not unsigned int. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: AM34: The current cacheflush routines operate by controlling tag regsDavid Howells4-2/+23
The current cache flush and invalidate routines operate by controlling the cache tag registers. Rename the files and add config items to select them. This makes it easier to support the use of other cache flush methods instead, such as the use of AM34's area purge registers, if available. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Reorder asm/cacheflush.h to put primitives firstDavid Howells1-44/+44
Reorder asm/cacheflush.h to put arch primitives first, before the main functions so that the main functions can be inline asm rather than #defines when non-trivial. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Provide a MN10300_CACHE_ENABLED config optionDavid Howells6-10/+13
Provide a MN10300_CACHE_ENABLED config option as inverted logic of MN10300_CACHE_DISABLED to make things simpler. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Cache: Split cache bits out of arch KconfigDavid Howells2-28/+33
Split the cache bits out of arch/mn10300/Kconfig as they're quite complex. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Remove monitor/JTAG functionsAkira Takeuchi4-55/+2
Remove the monitor trap function and the set_jtag_stub function as they're not really necessary. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Add CPU register bits for AM34Akira Takeuchi2-5/+74
Add CPU register declarations for the AM34 subarch. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Don't hard code the cacheline size in register defsAkira Takeuchi1-5/+9
Don't hard code the cacheline size in the cache control register definitions. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Move DMA engine control reg defs to MN103E010 processor directoryAkira Takeuchi2-86/+103
Move the DMA engine control register definitions to the MN103E010 processor directory so that the MN2WS0050 processor can have its own. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Differentiate AM33_2 and AM33_3 in configAkira Takeuchi1-2/+9
Differentiate AM33_2 and AM33_3 CPU cores in configuration. The MN103E010 processor contains an AM33_2 core. Whilst we're at it, prepare for AM34-based stuff by declaring AM34_2 too. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Provide the functions to fully disable maskable interruptsAkira Takeuchi1-0/+77
The local_irq_disable() function and co. merely raise the interrupt mask on the MN10300 arch to exclude normal interrupts. This still lets other, higher priority maskable interrupts through, such as are used to service gdbstub's serial port and the MN10300 on-chip serial port virtual FIFOs. Provide functions to allow the maskable interrupts to be fully disabled, which will exclude those interrupts. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Add reads[bwl]() and writes[bwl]()Akira Takeuchi1-0/+13
Add reads[bwl]() and writes[bwl]() for MN10300. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Don't cast away the volatile in test_bit()Akira Takeuchi1-1/+1
Don't cast away the volatile in test_bit()'s parameter when we change its type from const volatile void * so that we can dereference it. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: Prevent cnt32_to_63() from being preempted in sched_clock()David Howells1-0/+5
Prevent cnt32_to_63() from being preempted in sched_clock() because it may read its internal counter, get preempted, get delayed for more than the half period of the 'TSC' and then write the internal counter, thus corrupting it. Whilst some callers of sched_clock() have interrupts disabled or hold spinlocks, not all do, and so preemption must be held here. Note that sched_clock() is called from lockdep, but that shouldn't be a problem because although preempt_disable() calls into lockdep, lockdep has a recursion counter to deal with this. Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27mn10300: Use pci_claim_resourceDavid Howells1-10/+6
Instead of open-coding pci_find_parent_resource and request_resource, just call pci_claim_resource. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27bitops: Change the bitmap index from int to unsigned long [mn10300]Justin Chen2-8/+8
Change the index to unsigned long in all bitops for [mn10300] Signed-off-by: Justin Chen <justin.chen@hp.com> Reviewed-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27MN10300: BUG to BUG_ON changesStoyan Gaydarov5-10/+5
Signed-off-by: Stoyan Gaydarov <stoyboyker@gmail.com> Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-26Merge branches 'upstream/xenfs' and 'upstream/core' of ↵Linus Torvalds8-97/+576
git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen * 'upstream/xenfs' of git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen: xen/privcmd: make privcmd visible in domU xen/privcmd: move remap_domain_mfn_range() to core xen code and export. privcmd: MMAPBATCH: Fix error handling/reporting xenbus: export xen_store_interface for xenfs xen/privcmd: make sure vma is ours before doing anything to it xen/privcmd: print SIGBUS faults xen/xenfs: set_page_dirty is supposed to return true if it dirties xen/privcmd: create address space to allow writable mmaps xen: add privcmd driver xen: add variable hypercall caller xen: add xen_set_domain_pte() xen: add /proc/xen/xsd_{kva,port} to xenfs * 'upstream/core' of git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen: (29 commits) xen: include xen/xen.h for definition of xen_initial_domain() xen: use host E820 map for dom0 xen: correctly rebuild mfn list list after migration. xen: improvements to VIRQ_DEBUG output xen: set up IRQ before binding virq to evtchn xen: ensure that all event channels start off bound to VCPU 0 xen/hvc: only notify if we actually sent something xen: don't add extra_pages for RAM after mem_end xen: add support for PAT xen: make sure xen_max_p2m_pfn is up to date xen: limit extra memory to a certain ratio of base xen: add extra pages for E820 RAM regions, even if beyond mem_end xen: make sure xen_extra_mem_start is beyond all non-RAM e820 xen: implement "extra" memory to reserve space for pages not present at boot xen: Use host-provided E820 map xen: don't map missing memory xen: defer building p2m mfn structures until kernel is mapped xen: add return value to set_phys_to_machine() xen: convert p2m to a 3 level tree xen: make install_p2mtop_page() static ... Fix up trivial conflict in arch/x86/xen/mmu.c, and fix the use of 'reserve_early()' - in the new memblock world order it is now 'memblock_x86_reserve_range()' instead. Pointed out by Jeremy.
2010-10-26Merge branch 'release' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6 * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (53 commits) ACPI: install ACPI table handler before any dynamic tables being loaded ACPI / PM: Blacklist another machine that needs acpi_sleep=nonvs ACPI: Page based coalescing of I/O remappings optimization ACPI: Convert simple locking to RCU based locking ACPI: Pre-map 'system event' related register blocks ACPI: Add interfaces for ioremapping/iounmapping ACPI registers ACPI: Maintain a list of ACPI memory mapped I/O remappings ACPI: Fix ioremap size for MMIO reads and writes ACPI / Battery: Return -ENODEV for unknown values in get_property() ACPI / PM: Fix reference counting of power resources Subject: [PATCH] ACPICA: Fix Scope() op in module level code ACPI battery: support percentage battery remaining capacity ACPI: Make Embedded Controller command timeout delay configurable ACPI dock: move some functions to .init.text ACPI: thermal: remove unused limit code ACPI: static sleep_states[] and acpi_gts_bfs_check ACPI: remove dead code ACPI: delete dedicated MAINTAINERS entries for ACPI EC and BATTERY drivers ACPI: Only processor needs CPU_IDLE ACPICA: Update version to 20101013 ...
2010-10-26Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tileLinus Torvalds46-732/+1608
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: arch/tile: convert a BUG_ON to BUILD_BUG_ON arch/tile: make ptrace() work properly for TILE-Gx COMPAT mode arch/tile: support new info op generated by compiler arch/tile: minor whitespace/naming changes for string support files arch/tile: enable single-step support for TILE-Gx arch/tile: parameterize system PLs to support KVM port arch/tile: add Tilera's <arch/sim.h> header as an open-source header arch/tile: Bomb C99 comments to C89 comments in tile's <arch/sim_def.h> arch/tile: prevent corrupt top frame from causing backtracer runaway arch/tile: various top-level Makefile cleanups arch/tile: change lower bound on syscall error return to -4095 arch/tile: properly export __mb_incoherent for modules arch/tile: provide a definition of MAP_STACK kmemleak: add TILE to the list of supported architectures. char: hvc: check for error case arch/tile: Add a warning if we try to allocate too much vmalloc memory. arch/tile: update some comments to clarify register usage. arch/tile: use better "punctuation" for VMSPLIT_3_5G and friends arch/tile: Use <asm-generic/syscalls.h> tile: replace some BUG_ON checks with BUILD_BUG_ON checks
2010-10-26workqueues: s/ON_STACK/ONSTACK/Andrew Morton2-2/+2
Silly though it is, completions and wait_queue_heads use foo_ONSTACK (COMPLETION_INITIALIZER_ONSTACK, DECLARE_COMPLETION_ONSTACK, __WAIT_QUEUE_HEAD_INIT_ONSTACK and DECLARE_WAIT_QUEUE_HEAD_ONSTACK) so I guess workqueues should do the same thing. s/INIT_WORK_ON_STACK/INIT_WORK_ONSTACK/ s/INIT_DELAYED_WORK_ON_STACK/INIT_DELAYED_WORK_ONSTACK/ Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26m68k{nommu}/blackfin : remove old assembler-only flags bit definitionsPhilippe De Muyter3-26/+0
Long ago, PT_TRACESYS_OFF and friends were introduced as hard defines to avoid straight constants in assembler parts of linux m68k. They are not used anymore, and were not updated to follow changes in linux kernel. Remove them. When similar constants are needed, they are now generated using asm-offsets.c. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Acked-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26replace nested max/min macros with {max,min}3 macroHagen Paul Pfeifer3-5/+3
Use the new {max,min}3 macros to save some cycles and bytes on the stack. This patch substitutes trivial nested macros with their counterpart. Signed-off-by: Hagen Paul Pfeifer <hagen@jauu.net> Cc: Joe Perches <joe@perches.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Hartley Sweeten <hsweeten@visionengravers.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: Roland Dreier <rolandd@cisco.com> Cc: Sean Hefty <sean.hefty@intel.com> Cc: Pekka Enberg <penberg@cs.helsinki.fi> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26um: migrate from __do_IRQ() to generic_handle_irq()Richard Weinberger2-11/+7
This patch removes __do_IRQ() from user mode linux. __do_IRQ is deprecated. Signed-off-by: Richard Weinberger <richard@nod.at> Cc: Jeff Dike <jdike@addtoit.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26uml: fix CONFIG_STATIC_LINK=y build failure with newer glibcRoland McGrath2-2/+29
With glibc 2.11 or later that was built with --enable-multi-arch, the UML link fails with undefined references to __rel_iplt_start and similar symbols. In recent binutils, the default linker script defines these symbols (see ld --verbose). Fix the UML linker scripts to match the new defaults for these sections. Signed-off-by: Roland McGrath <roland@redhat.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26uml: define CONFIG_NO_DMAFUJITA Tomonori3-113/+3
I think that it's better to detect DMA misuse at build time rather than calling BUG_ON. Architectures that can't do DMA need to define CONFIG_NO_DMA. Thanks to Sam Ravnborg for explaining how CONFIG_NO_DMA and CONFIG_HAS_DMA work: http://marc.info/?l=linux-kernel&m=128359913825550&w=2 HAS_DMA is defined like this: config HAS_DMA boolean depends on !NO_DMA default y So to set HAS_DMA to true an arch should do: 1) Do not define NO_DMA 2) Define NO_DMA abd set it to 'n' Must archs - including um - used principle 1). In the um case we want to say that we do NOT have any DMA. This can be done in two ways. a) define NO_DMA and set it to 'y' b) redefine HAS_DMA and set it to 'n'. The patch you provided used principle b) where other archs use principle a). So I suggest you should use principle a) for um too. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: Miklos Szeredi <miklos@szeredi.hu> Cc: Jeff Dike <jdike@addtoit.com> Cc: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26alpha: use single HAE window on T2 core logic (gamma, sable)Ivan Kokshaysky4-40/+30
T2 are the only alpha SMP systems that do HAE switching at runtime, which is fundamentally racy on SMP. This patch limits MMIO space on T2 to HAE0 only, like we did on MCPCIA (rawhide) long ago. This leaves us with only 112 Mb of PCI MMIO (128 Mb HAE aperture minus 16 Mb reserved for EISA), but since linux PCI allocations are reasonably tight, it should be enough for sane hardware configurations. Also, fix a typo in MCPCIA_FROB_MMIO macro which shouldn't call set_hae() if MCPCIA_ONE_HAE_WINDOW is defined. It's more for correctness, as set_hae() is a no-op anyway in that case. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26alpha: enable ARCH_DMA_ADDR_T_64BITFUJITA Tomonori1-0/+3
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Richard Henderson <rth@twiddle.net> Cc: Matt Turner <mattst88@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26x86: access_error API cleanupMichel Lespinasse1-3/+3
access_error() already takes error_code as an argument, so there is no need for an additional write flag. Signed-off-by: Michel Lespinasse <walken@google.com> Acked-by: Rik van Riel <riel@redhat.com> Cc: Nick Piggin <nickpiggin@yahoo.com.au> Acked-by: Wu Fengguang <fengguang.wu@intel.com> Cc: Ying Han <yinghan@google.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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