summaryrefslogtreecommitdiffstats
path: root/arch/xtensa/include/asm/traps.h
AgeCommit message (Collapse)AuthorFilesLines
2018-12-03xtensa: drop unused field from the struct exc_tableMax Filippov1-2/+0
exc_table::syscall_save and corresponding macro EXC_TABLE_SYSCALL_SAVE have never been used by the xtensa code. Drop them. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-16xtensa: implement early_trap_initMax Filippov1-0/+12
Paging on xtensa architecture requires functioning exception handling because hardware cannot transparently access page tables that are not currently mapped by TLB. Exception handling is set up late in the initialization process, but working paging is needed for KASAN. Provide early_trap_init that sets up minimal exception handling sufficient for KASAN to work. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-12-16xtensa: clean up exception handling structureMax Filippov1-0/+23
Instead of using flat array of longs use normal C structure and generate EXC_TABLE_* constants in the asm-offsets.c Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-03-11xtensa: support hardware breakpoints/watchpointsMax Filippov1-0/+8
Use perf framework to manage hardware instruction and data breakpoints. Add two new ptrace calls: PTRACE_GETHBPREGS and PTRACE_SETHBPREGS to query and set instruction and data breakpoints. Address bit 0 choose instruction (0) or data (1) break register, bits 31..1 are the register number. Both calls transfer two 32-bit words: address (0) and control (1). Instruction breakpoint contorl word is 0 to clear breakpoint, 1 to set. Data breakpoint control word bit 31 is 'trigger on store', bit 30 is 'trigger on load, bits 29..0 are length. Length 0 is used to clear a breakpoint. To set a breakpoint length must be a power of 2 in the range 1..64 and the address must be length-aligned. Introduce new thread_info flag: TIF_DB_DISABLED. Set it if debug exception is raised by the kernel code accessing watched userspace address and disable corresponding data breakpoint. On exit to userspace check that flag and, if set, restore all data breakpoints. Handle debug exceptions raised with PS.EXCM set. This may happen when window overflow/underflow handler or fast exception handler hits data breakpoint, in which case save and disable all data breakpoints, single-step faulting instruction and restore data breakpoints. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-03-11xtensa: use context structure for debug exceptionsMax Filippov1-0/+9
With implementation of data breakpoints debug exceptions raised when PS.EXCM is set need to be handled, e.g. window overflow code can write to watched userspace address. Currently debug exception handler uses EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be available when PS.EXCM is set and more space will be needed to save additional state. Reorganize debug context: create per-CPU structure debug_table instance and store its address in the EXCSAVE<debug level> instead of debug_exception function address. Expand this structure when more save space is needed. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-08-17xtensa: fix kernel register spillingMax Filippov1-10/+19
call12 can't be safely used as the first call in the inline function, because the compiler does not extend the stack frame of the bounding function accordingly, which may result in corruption of local variables. If a call needs to be done, do call8 first followed by call12. For pure assembly code in _switch_to increase stack frame size of the bounding function. Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-01-25xtensa: introduce spill_registers_kernel macroMax Filippov1-16/+28
Most in-kernel users want registers spilled on the kernel stack and don't require PS.EXCM to be set. That means that they don't need fixup routine and could reuse regular window overflow mechanism for that, which makes spill routine very simple. Cc: stable@vger.kernel.org Suggested-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-01-14xtensa: add SMP supportMax Filippov1-0/+1
This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
2013-05-09xtensa: clean up stpill_registersMax Filippov1-3/+2
- remove unused asm parameters; - fix EXCM bit setting in the PS SR during _spill_registers call. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
2013-02-23xtensa: move spill_registers to traps.hMax Filippov1-0/+24
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
2012-12-18xtensa: add trap_set_handler functionMax Filippov1-0/+23
trap_set_handler sets new C-handler in the exception table and returns previous handler. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>