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2015-11-09xtensa: support DMA to high memoryMax Filippov1-3/+8
- don't bugcheck if high memory page is passed to xtensa_map_page; - turn empty dcache flush macros into functions so that they could be passed as function parameters; - use kmap_atomic to map high memory pages for cache invalidation/ flushing performed by xtensa_sync_single_for_{cpu,device}. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-11-03Revert "xtensa: cache inquiry and unaligned cache handling functions"Max Filippov1-95/+0
Drop unaligned dcache management functions as they are no longer used. This reverts commit bd974240c9a7 ("xtensa: cache inquiry and unaligned cache handling functions"). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-10-21xtensa: nommu: don't build most of the cache flushing codeMax Filippov1-2/+3
Most cache flushing code is only relevant for MMU. Don't build it for nommu configuration. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-10-21xtensa: nommu: provide __invalidate_dcache_page_alias stubMax Filippov1-0/+2
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-08-14xtensa: implement clear_user_highpage and copy_user_highpageMax Filippov1-0/+2
Existing clear_user_page and copy_user_page cannot be used with highmem because they calculate physical page address from its virtual address and do it incorrectly in case of high memory page mapped with kmap_atomic. Also kmap is not needed, as most likely userspace mapping color would be different from the kmapped color. Provide clear_user_highpage and copy_user_highpage functions that determine if temporary mapping is needed for the pages. Move most of the logic of the former clear_user_page and copy_user_page to xtensa/mm/cache.c only leaving temporary mapping setup, invalidation and clearing/copying in the xtensa/mm/misc.S. Rename these functions to clear_page_alias and copy_page_alias. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-01-14xtensa: add SMP supportMax Filippov1-15/+25
This is largely based on SMP code from the xtensa-2.6.29-smp tree by Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly other Tensilica folks). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
2012-12-18xtensa: clean up files to make them code-style compliantChris Zankel1-1/+2
Remove heading and trailing spaces, trim trailing lines, and wrap lines that are longer than 80 characters. Signed-off-by: Chris Zankel <chris@zankel.net>
2012-10-15xtensa: reorganize SR referencingMax Filippov1-1/+1
- reference SRs by names where possible, not by numbers; - get rid of __stringify around SR names where possible; - remove unneeded SR names from asm/regs.h; - add SREG_ prefix to remaining SR names; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
2010-05-01xtensa: Fix FLUSH_DCACHE macro for some variants.Chris Zankel1-0/+1
Define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE also for processor configurations that don't have cache-aliasing. Signed-off-by: Chris Zankel <chris@zankel.net>
2009-11-26block: add helpers to run flush_dcache_page() against a bio and a request's ↵Ilya Loginov1-0/+1
pages Mtdblock driver doesn't call flush_dcache_page for pages in request. So, this causes problems on architectures where the icache doesn't fill from the dcache or with dcache aliases. The patch fixes this. The ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE symbol was introduced to avoid pointless empty cache-thrashing loops on architectures for which flush_dcache_page() is a no-op. Every architecture was provided with this flush pages on architectires where ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE is equal 1 or do nothing otherwise. See "fix mtd_blkdevs problem with caches on some architectures" discussion on LKML for more information. Signed-off-by: Ilya Loginov <isloginov@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Peter Horton <phorton@bitbox.co.uk> Cc: "Ed L. Cashin" <ecashin@coraid.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
2009-06-22xtensa: cache inquiry and unaligned cache handling functionsOskar Schirmer1-0/+95
The existing xtensa cache handling functions work on page-aligned memory regions. These functions are needed for the s6000 dma engine which can work on a byte-granularity. Signed-off-by: Oskar Schirmer <os@emlix.com> Cc: Johannes Weiner <jw@emlix.com> Cc: Daniel Glockner <dg@emlix.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Chris Zankel <chris@zankel.net>
2009-04-02xtensa: nommu supportJohannes Weiner1-3/+7
Add support for !CONFIG_MMU setups. Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>
2008-11-06xtensa: move headers files to arch/xtensa/includeChris Zankel1-0/+155
Move all header files for xtensa to arch/xtensa/include and platform and variant header files to the appropriate arch/xtensa/platforms/ and arch/xtensa/variants/ directories. Moving the files gets also rid of all uses of symlinks in the Makefile. This has been completed already for the majority of the architectures and xtensa is one out of six missing. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Chris Zankel <chris@zankel.net>