Age | Commit message (Expand) | Author | Files | Lines |
2018-01-31 | Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds | 2 | -2/+1 |
2018-01-31 | Merge tag 'dma-mapping-4.16' of git://git.infradead.org/users/hch/dma-mapping | Linus Torvalds | 3 | -39/+2 |
2018-01-29 | Merge tag 'init_task-20180117' of git://git.kernel.org/pub/scm/linux/kernel/g... | Linus Torvalds | 1 | -2/+0 |
2018-01-15 | dma-direct: rename dma_noop to dma_direct | Christoph Hellwig | 1 | -1/+1 |
2018-01-15 | dma-mapping: provide a generic asm/dma-mapping.h | Christoph Hellwig | 2 | -30/+1 |
2018-01-09 | Construct init thread stack in the linker script rather than by union | David Howells | 1 | -2/+0 |
2018-01-09 | riscv: remove the unused dma_capable helper | Christoph Hellwig | 1 | -8/+0 |
2018-01-07 | riscv: rename SR_* constants to match the spec | Christoph Hellwig | 6 | -17/+17 |
2018-01-07 | riscv: remove CONFIG_MMU ifdefs | Christoph Hellwig | 4 | -24/+0 |
2018-01-07 | RISC-V: Make __NR_riscv_flush_icache visible to userspace | Palmer Dabbelt | 5 | -30/+27 |
2018-01-07 | RISC-V: Add a basic defconfig | Karsten Merker | 1 | -0/+75 |
2017-12-11 | RISC-V: Remove unused CONFIG_HVC_RISCV_SBI code | Palmer Dabbelt | 1 | -11/+0 |
2017-12-11 | RISC-V: Resurrect smp_mb__after_spinlock() | Palmer Dabbelt | 1 | -0/+19 |
2017-12-11 | RISC-V: Logical vs Bitwise typo | Dan Carpenter | 1 | -1/+1 |
2017-12-05 | bpf: correct broken uapi for BPF_PROG_TYPE_PERF_EVENT program type | Hendrik Brueckner | 1 | -0/+1 |
2017-12-04 | riscv: use linux/uaccess.h, not asm/uaccess.h... | Al Viro | 2 | -2/+1 |
2017-12-01 | RISC-V: Fixes for clean allmodconfig build | Palmer Dabbelt | 12 | -21/+39 |
2017-12-01 | RISC-V: __io_writes should respect the length argument | Palmer Dabbelt | 1 | -1/+1 |
2017-12-01 | RISC-V: User-Visible Changes | Palmer Dabbelt | 19 | -34/+392 |
2017-12-01 | RISC-V: __io_writes should respect the length argument | Palmer Dabbelt | 1 | -1/+1 |
2017-11-30 | RISC-V: Clean up an unused include | Palmer Dabbelt | 1 | -1/+0 |
2017-11-30 | RISC-V: Allow userspace to flush the instruction cache | Andrew Waterman | 8 | -0/+105 |
2017-11-30 | RISC-V: Flush I$ when making a dirty page executable | Andrew Waterman | 8 | -30/+174 |
2017-11-30 | RISC-V: Add missing include | Olof Johansson | 1 | -0/+1 |
2017-11-30 | RISC-V: Use define for get_cycles like other architectures | Olof Johansson | 1 | -1/+2 |
2017-11-30 | RISC-V: Provide stub of setup_profiling_timer() | Olof Johansson | 1 | -0/+7 |
2017-11-30 | RISC-V: Export some expected symbols for modules | Olof Johansson | 3 | -0/+6 |
2017-11-30 | RISC-V: move empty_zero_page definition to C and export it | Olof Johansson | 2 | -3/+3 |
2017-11-30 | RISC-V: io.h: type fixes for warnings | Olof Johansson | 2 | -8/+10 |
2017-11-30 | RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros | Olof Johansson | 2 | -9/+9 |
2017-11-30 | RISC-V: use generic serial.h | Olof Johansson | 1 | -0/+1 |
2017-11-28 | RISC-V: remove spin_unlock_wait() | Palmer Dabbelt | 1 | -9/+0 |
2017-11-28 | RISC-V: `sfence.vma` orderes the instruction cache | Palmer Dabbelt | 1 | -1/+4 |
2017-11-28 | RISC-V: Add READ_ONCE in arch_spin_is_locked() | Palmer Dabbelt | 1 | -1/+1 |
2017-11-28 | RISC-V: __test_and_op_bit_ord should be strongly ordered | Palmer Dabbelt | 1 | -1/+1 |
2017-11-28 | RISC-V: Remove smb_mb__{before,after}_spinlock() | Palmer Dabbelt | 1 | -8/+0 |
2017-11-28 | RISC-V: Remove __smp_bp__{before,after}_atomic | Palmer Dabbelt | 1 | -15/+0 |
2017-11-28 | RISC-V: Comment on why {,cmp}xchg is ordered how it is | Palmer Dabbelt | 1 | -2/+7 |
2017-11-28 | RISC-V: Remove unused arguments from ATOMIC_OP | Palmer Dabbelt | 1 | -47/+47 |
2017-11-27 | RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpu | Andrew Waterman | 6 | -1/+113 |
2017-11-27 | RISC-V: Remove __vdso_cmpxchg{32,64} symbol versions | Palmer Dabbelt | 1 | -2/+0 |
2017-11-15 | Merge tag 'riscv-for-linus-4.15-arch-v9-premerge' of git://git.kernel.org/pub... | Linus Torvalds | 102 | -0/+9776 |
2017-09-26 | RISC-V: Build Infrastructure | Palmer Dabbelt | 9 | -0/+579 |
2017-09-26 | RISC-V: User-facing API | Palmer Dabbelt | 27 | -0/+1687 |
2017-09-26 | RISC-V: Paging and MMU | Palmer Dabbelt | 8 | -0/+1192 |
2017-09-26 | RISC-V: Device, timer, IRQs, and the SBI | Palmer Dabbelt | 9 | -0/+566 |
2017-09-26 | RISC-V: Task implementation | Palmer Dabbelt | 9 | -0/+1243 |
2017-09-26 | RISC-V: ELF and module implementation | Palmer Dabbelt | 4 | -0/+187 |
2017-09-26 | RISC-V: Generic library routines and assembly | Palmer Dabbelt | 11 | -0/+1389 |
2017-09-26 | RISC-V: Atomic and Locking Code | Palmer Dabbelt | 10 | -0/+1423 |