linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2019-10-28	RISC-V: Add PCIe I/O BAR memory mapping	Yash Shah	2	-1/+13
2019-10-28	riscv: for C functions called only from assembly, mark with __visible	Paul Walmsley	5	-8/+8
2019-10-28	riscv: fp: add missing __user pointer annotations	Paul Walmsley	1	-2/+2
2019-10-28	riscv: add missing header file includes	Paul Walmsley	13	-0/+17
2019-10-28	riscv: mark some code and data as file-static	Paul Walmsley	2	-2/+2
2019-10-28	riscv: init: merge split string literals in preprocessor directive	Paul Walmsley	1	-2/+1
2019-10-28	riscv: add prototypes for assembly language functions from head.S	Paul Walmsley	5	-0/+29
2019-10-25	riscv: cleanup do_trap_break	Christoph Hellwig	1	-20/+6
2019-10-23	riscv: cleanup <asm/bug.h>	Christoph Hellwig	1	-13/+3
2019-10-23	riscv: Fix undefined reference to vmemmap_populate_basepages	Kefeng Wang	1	-1/+1
2019-10-23	riscv: Fix implicit declaration of 'page_to_section'	Kefeng Wang	1	-4/+1
2019-10-23	riscv: fix fs/proc/kcore.c compilation with sparsemem enabled	David Abdurachmanov	1	-2/+0
2019-10-15	RISC-V: fix virtual address overlapped in FIXADDR_START and VMEMMAP_START	Greentime Hu	1	-8/+8
2019-10-14	riscv: tlbflush: remove confusing comment on local_flush_tlb_all()	Paul Walmsley	1	-4/+0
2019-10-14	riscv: dts: HiFive Unleashed: add default chosen/stdout-path	Paul Walmsley	1	-0/+1
2019-10-14	riscv: remove the switch statement in do_trap_break()	Vincent Chen	1	-11/+11
2019-10-09	RISC-V: entry: Remove unneeded need_resched() loop	Valentin Schneider	1	-2/+1
2019-10-07	riscv: Correct the handling of unexpected ebreak in do_trap_break()	Vincent Chen	1	-3/+3
2019-10-07	riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()	Vincent Chen	1	-1/+1
2019-10-07	riscv: avoid kernel hangs when trapped in BUG()	Vincent Chen	1	-3/+3
2019-10-01	riscv: Fix memblock reservation for device tree blob	Albert Ou	1	-1/+11
2019-10-01	RISC-V: Clear load reservations while restoring hart contexts	Palmer Dabbelt	2	-1/+21
2019-09-27	Merge tag 'riscv/for-v5.4-rc1-b' of git://git.kernel.org/pub/scm/linux/kernel...	Linus Torvalds	9	-19/+73
2019-09-26	mm: treewide: clarify pgtable_page_{ctor,dtor}() naming	Mark Rutland	1	-1/+1
2019-09-24	riscv: make mmap allocation top-down by default	Alexandre Ghiti	1	-0/+12
2019-09-24	mm: consolidate pgtable_cache_init() and pgd_cache_init()	Mike Rapoport	1	-5/+0
2019-09-24	mm: remove quicklist page table caches	Nicholas Piggin	1	-4/+0
2019-09-20	riscv: Avoid interrupts being erroneously enabled in handle_exception()	Vincent Chen	1	-1/+5
2019-09-20	riscv: dts: sifive: Drop "clock-frequency" property of cpu nodes	Bin Meng	1	-3/+0
2019-09-20	riscv: dts: sifive: Add ethernet0 to the aliases node	Bin Meng	1	-0/+1
2019-09-20	Merge tag 'kbuild-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/masa...	Linus Torvalds	2	-1/+2
2019-09-20	RISC-V: Export kernel symbols for kvm	Atish Patra	2	-0/+2
2019-09-20	arch/riscv: disable excess harts before picking main boot hart	Xiang Wang	1	-3/+5
2019-09-19	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig	Anup Patel	2	-0/+22
2019-09-19	RISC-V: Fix building error when CONFIG_SPARSEMEM_MANUAL=y	Greentime Hu	1	-12/+12
2019-09-19	riscv: dts: Add DT support for SiFive FU540 PWM driver	Yash Shah	2	-0/+26
2019-09-16	Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	24	-110/+369
2019-09-16	Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...	Linus Torvalds	2	-0/+4
2019-09-13	riscv: modify the Image header to improve compatibility with the ARM64 header	Paul Walmsley	2	-8/+8
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	3	-30/+45
2019-09-05	riscv: don't use the rdtime(h) pseudo-instructions	Christoph Hellwig	1	-23/+21
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	4	-8/+1
2019-09-05	riscv: optimize send_ipi_single	Christoph Hellwig	1	-1/+7
2019-09-05	riscv: cleanup send_ipi_mask	Christoph Hellwig	1	-9/+7
2019-09-05	riscv: refactor the IPI code	Christoph Hellwig	1	-24/+31
2019-09-05	riscv: Add support for perf registers sampling	Mao Han	4	-0/+89
2019-09-04	riscv: Add perf callchain support	Mao Han	4	-3/+101
2019-08-30	riscv: add arch/riscv/Kbuild	Masahiro Yamada	2	-1/+4
2019-08-30	RISC-V: Implement sparsemem	Logan Gunthorpe	5	-0/+57
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng	6	-21/+16