linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Expand)	Author	Files	Lines
2020-01-23	riscv: mm: add support for CONFIG_DEBUG_VIRTUAL	Zong Li	2	-0/+39
2020-01-22	riscv: Add KASAN support	Nick Hu	2	-0/+110
2020-01-03	riscv: mm: use __pa_symbol for kernel symbols	Zong Li	1	-6/+6
2019-12-27	riscv: export flush_icache_all to modules	Olof Johansson	1	-0/+1
2019-12-20	riscv: move sifive_l2_cache.c to drivers/soc	Christoph Hellwig	2	-179/+0
2019-12-04	Merge tag 'riscv/for-v5.5-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel...	Linus Torvalds	1	-0/+32
2019-11-28	Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremap	Linus Torvalds	2	-85/+1
2019-11-22	Merge branch 'next/misc2' into for-next	Paul Walmsley	1	-0/+32
2019-11-22	Merge branch 'next/nommu' into for-next	Paul Walmsley	6	-15/+41
2019-11-22	Merge branch 'next/misc' into for-next	Paul Walmsley	1	-9/+4
2019-11-22	RISC-V: Add address map dumper	Yash Shah	1	-0/+32
2019-11-17	riscv: add nommu support	Christoph Hellwig	4	-4/+18
2019-11-13	riscv: implement remote sfence.i using IPIs	Christoph Hellwig	1	-6/+18
2019-11-12	riscv: Use PMD_SIZE to replace PTE_PARENT_SIZE	Zong Li	1	-9/+4
2019-11-11	riscv: use the generic ioremap code	Christoph Hellwig	2	-85/+0
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	2	-5/+5
2019-10-29	RISC-V: Issue a tlb page flush if possible	Atish Patra	1	-1/+4
2019-10-29	RISC-V: Issue a local tlbflush if possible.	Atish Patra	1	-2/+17
2019-10-29	RISC-V: Do not invoke SBI call if cpumask is empty	Atish Patra	1	-0/+3
2019-10-28	riscv: add missing header file includes	Paul Walmsley	1	-0/+1
2019-10-28	riscv: mark some code and data as file-static	Paul Walmsley	1	-1/+1
2019-10-28	riscv: init: merge split string literals in preprocessor directive	Paul Walmsley	1	-2/+1
2019-10-28	riscv: add prototypes for assembly language functions from head.S	Paul Walmsley	2	-0/+4
2019-10-23	riscv: Fix undefined reference to vmemmap_populate_basepages	Kefeng Wang	1	-1/+1
2019-10-01	riscv: Fix memblock reservation for device tree blob	Albert Ou	1	-1/+11
2019-09-05	riscv: move the TLB flush logic out of line	Christoph Hellwig	2	-0/+38
2019-09-05	riscv: cleanup riscv_cpuid_to_hartid_mask	Christoph Hellwig	1	-1/+0
2019-08-30	RISC-V: Implement sparsemem	Logan Gunthorpe	1	-0/+10
2019-08-30	riscv: Using CSR numbers to access CSRs	Bin Meng	2	-7/+2
2019-07-18	Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	4	-68/+315
2019-07-09	RISC-V: Setup initial page tables in two stages	Anup Patel	1	-52/+255
2019-07-08	Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...	Linus Torvalds	1	-3/+3
2019-07-04	riscv: remove free_initrd_mem	Christoph Hellwig	1	-5/+0
2019-07-04	riscv: ccache: Remove unused variable	Yash Shah	1	-4/+7
2019-07-03	riscv: Introduce huge page support for 32/64bit kernel	Alexandre Ghiti	2	-0/+46
2019-07-01	RISC-V: Fix memory reservation in setup_bootmem()	Anup Patel	1	-7/+7
2019-06-26	riscv: mm: Fix code comment	ShihPo Hung	1	-3/+0
2019-06-17	Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...	Linus Torvalds	1	-0/+13
2019-06-17	riscv: mm: synchronize MMU after pte change	ShihPo Hung	1	-0/+13
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	3	-27/+3
2019-05-29	signal/riscv: Remove tsk parameter from do_trap	Eric W. Biederman	1	-3/+3
2019-05-24	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120	Thomas Gleixner	2	-28/+2
2019-05-21	treewide: Add SPDX license identifier - Makefile/Kconfig	Thomas Gleixner	1	-0/+1
2019-05-19	Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...	Linus Torvalds	5	-6/+310
2019-05-16	riscv: fix locking violation in page fault handler	Andreas Schwab	1	-1/+2
2019-05-16	RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs	Yash Shah	2	-0/+176
2019-05-16	riscv: move switch_mm to its own file	Gary Guo	2	-0/+70
2019-05-16	riscv: move flush_icache_{all,mm} to cacheflush.c	Gary Guo	1	-0/+61
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-5/+1
2019-05-14	riscv: switch over to generic free_initmem()	Mike Rapoport	1	-5/+0