summaryrefslogtreecommitdiffstats
path: root/arch/riscv/mm
AgeCommit message (Expand)AuthorFilesLines
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig2-0/+38
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig1-1/+0
2019-08-30RISC-V: Implement sparsememLogan Gunthorpe1-0/+10
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng2-7/+2
2019-07-18Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds4-68/+315
2019-07-09RISC-V: Setup initial page tables in two stagesAnup Patel1-52/+255
2019-07-08Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds1-3/+3
2019-07-04riscv: remove free_initrd_memChristoph Hellwig1-5/+0
2019-07-04riscv: ccache: Remove unused variableYash Shah1-4/+7
2019-07-03riscv: Introduce huge page support for 32/64bit kernelAlexandre Ghiti2-0/+46
2019-07-01RISC-V: Fix memory reservation in setup_bootmem()Anup Patel1-7/+7
2019-06-26riscv: mm: Fix code commentShihPo Hung1-3/+0
2019-06-17Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-0/+13
2019-06-17riscv: mm: synchronize MMU after pte changeShihPo Hung1-0/+13
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner3-27/+3
2019-05-29signal/riscv: Remove tsk parameter from do_trapEric W. Biederman1-3/+3
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner2-28/+2
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
2019-05-19Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds5-6/+310
2019-05-16riscv: fix locking violation in page fault handlerAndreas Schwab1-1/+2
2019-05-16RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah2-0/+176
2019-05-16riscv: move switch_mm to its own fileGary Guo2-0/+70
2019-05-16riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo1-0/+61
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel1-5/+1
2019-05-14riscv: switch over to generic free_initmem()Mike Rapoport1-5/+0
2019-04-10RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systemsAnup Patel1-0/+8
2019-03-26RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel2-0/+34
2019-02-21RISC-V: Free-up initrd in free_initrd_mem()Anup Patel1-1/+2
2019-02-21RISC-V: Implement compile-time fixed mappingsAnup Patel1-0/+34
2019-02-21RISC-V: Move setup_vm() to mm/init.cAnup Patel1-0/+49
2019-02-21RISC-V: Move setup_bootmem() to mm/init.cAnup Patel1-0/+70
2019-01-23riscv: fixup max_low_pfn with PFN_DOWN.Guo Ren1-1/+2
2018-10-31mm: remove include/linux/bootmem.hMike Rapoport1-2/+1
2018-10-31memblock: rename free_all_bootmem to memblock_free_allMike Rapoport1-1/+1
2018-10-22RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremapVincent Chen1-1/+1
2018-08-17mm: convert return type of handle_mm_fault() caller to vm_fault_tSouptick Joarder1-1/+2
2018-07-04RISC-V: Add conditional macro for zone of DMA32Zong Li1-0/+2
2018-02-07Merge tag 'riscv-for-linus-4.16-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds2-6/+10
2018-01-31Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds1-1/+0
2018-01-30riscv: rename sptbr to satpChristoph Hellwig1-0/+4
2018-01-30riscv: don't read back satp in paging_initChristoph Hellwig1-2/+0
2018-01-30riscv: add ZONE_DMA32Christoph Hellwig1-4/+6
2018-01-07riscv: rename SR_* constants to match the specChristoph Hellwig1-1/+1
2017-12-04riscv: use linux/uaccess.h, not asm/uaccess.h...Al Viro1-1/+0
2017-12-01RISC-V: Fixes for clean allmodconfig buildPalmer Dabbelt1-1/+1
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman2-0/+24
2017-11-30RISC-V: io.h: type fixes for warningsOlof Johansson1-1/+1
2017-09-26RISC-V: Build InfrastructurePalmer Dabbelt1-0/+4
2017-09-26RISC-V: Paging and MMUPalmer Dabbelt1-0/+282
2017-09-26RISC-V: Device, timer, IRQs, and the SBIPalmer Dabbelt1-0/+92