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path: root/arch/riscv/kernel
AgeCommit message (Expand)AuthorFilesLines
2019-01-03Remove 'type' argument from access_ok() functionLinus Torvalds1-2/+2
2018-12-21RISC-V: Move from EARLY_PRINTK to SBI earlyconPalmer Dabbelt1-28/+0
2018-12-21riscv: remove unused variable in ftraceDavid Abdurachmanov1-1/+0
2018-12-21RISC-V: add of_node_put()Yangtao Li1-0/+1
2018-12-21RISC-V: Fix of_node_* refcountAtish Patra5-1/+20
2018-12-17RISC-V: Remove EARLY_PRINTK supportAnup Patel1-28/+0
2018-11-30Merge tag 'trace-v4.20-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/...Linus Torvalds1-12/+2
2018-11-27riscv/function_graph: Simplify with function_graph_enter()Steven Rostedt (VMware)1-12/+2
2018-11-20RISC-V: recognize S/U mode bits in print_isaPatrick Stählin1-3/+6
2018-11-20RISC-V: Build flat and compressed kernel imagesAnup Patel2-1/+11
2018-11-12RISC-V: Silence some module warnings on 32-bitOlof Johansson1-6/+6
2018-10-31RISC-V: properly determine hardware capsAndreas Schwab1-3/+5
2018-10-22RISC-V: SMP cleanup and new featuresPalmer Dabbelt7-47/+195
2018-10-22RISC-V: Fix some RV32 bugs and build failuresPalmer Dabbelt1-0/+3
2018-10-22riscv: Add support to no-FPU systemsPalmer Dabbelt6-115/+168
2018-10-22RISC-V: remove the unused return_to_handler exportChristoph Hellwig1-1/+0
2018-10-22RISC-V: Add FP register ptrace support for gdb.Jim Wilson1-0/+52
2018-10-22RISC-V: Mask out the F extension on systems without DPalmer Dabbelt1-0/+7
2018-10-22RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt1-7/+0
2018-10-22RISC-V: Show IPI statsAnup Patel2-7/+40
2018-10-22RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfoAnup Patel1-4/+6
2018-10-22RISC-V: Use Linux logical CPU number instead of hartidAtish Patra5-22/+45
2018-10-22RISC-V: Add logical CPU indexing for RISC-VAtish Patra2-0/+23
2018-10-22RISC-V: Use WRITE_ONCE instead of direct accessAtish Patra1-2/+3
2018-10-22RISC-V: Use mmgrab()Palmer Dabbelt1-1/+2
2018-10-22RISC-V: Rename im_okay_therefore_i_am to found_boot_cpuPalmer Dabbelt1-4/+5
2018-10-22RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2-3/+6
2018-10-22RISC-V: Disable preemption before enabling interruptsAtish Patra1-1/+5
2018-10-22RISC-V: Comment on the TLB flush in smp_callin()Palmer Dabbelt1-0/+4
2018-10-22RISC-V: Filter ISA and MMU values in cpuinfoPalmer Dabbelt1-7/+61
2018-10-22RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt1-7/+0
2018-10-22RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel2-3/+2
2018-10-22RISC-V: Use swiotlb on RV64 onlyZong Li1-0/+3
2018-10-22Auto-detect whether a FPU existsAlan Kao3-3/+15
2018-10-22Allow to disable FPU supportAlan Kao3-2/+9
2018-10-22Refactor FPU code in signal setup/return proceduresAlan Kao1-27/+41
2018-10-22Extract FPU context operations from entry.SAlan Kao3-87/+107
2018-10-02RISCV: Fix end PFN for low memoryAtish Patra1-1/+1
2018-09-04riscv: Do not overwrite initrd_start and initrd_endGuenter Roeck1-7/+0
2018-08-28RISC-V: Use a less ugly workaround for unused variable warningsPalmer Dabbelt1-14/+1
2018-08-20RISC-V: Define sys_riscv_flush_icache when SMP=nPalmer Dabbelt1-2/+10
2018-08-13RISC-V: Fix !CONFIG_SMP compilation errorAtish Patra1-1/+0
2018-08-13RISC-V: Add the directive for alignment of stvec's valueZong Li1-0/+2
2018-08-13clocksource: new RISC-V SBI timer driverPalmer Dabbelt3-9/+4
2018-08-13RISC-V: implement low-level interrupt handlingChristoph Hellwig2-11/+45
2018-08-13RISC-V: simplify software interrupt / IPI codeChristoph Hellwig1-4/+2
2018-08-13RISC-V: remove timer leftoversChristoph Hellwig1-21/+0
2018-08-13RISC-V: Add early printk support via the SBI consolePalmer Dabbelt1-0/+27
2018-08-13RISC-V: Don't increment sepc after breakpoint.Jim Wilson1-1/+0
2018-08-13RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSOPalmer Dabbelt1-2/+2