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2022-04-26riscv: compat: syscall: Add entry.S implementationGuo Ren1-2/+16
2022-03-25Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-0/+4
2022-03-22RISC-V: Add support for restartable sequenceVincent Chen1-0/+4
2022-02-24riscv: fix oops caused by irqsoff latency tracerChangbin Du1-5/+5
2021-11-01Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linu...Linus Torvalds1-5/+0
2021-10-26irq: riscv: perform irqentry in entry codeMark Rutland1-2/+1
2021-09-30riscv: rely on core code to keep thread_info::cpu updatedArd Biesheuvel1-5/+0
2021-07-06riscv: add VMAP_STACK overflow detectionTong Tiangen1-0/+108
2021-05-06Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-2/+4
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen1-2/+4
2021-04-15riscv: keep interrupts disabled for BREAKPOINT exceptionJisheng Zhang1-0/+3
2021-04-01riscv,entry: fix misaligned base for excp_vect_tableZihao Yu1-0/+1
2021-01-12riscv: Trace irq on only interrupt is enabledAtish Patra1-3/+3
2021-01-07riscv: Enable interrupts during syscalls with M-ModeDamien Le Moal1-0/+9
2021-01-07riscv: return -ENOSYS for syscall -1Andreas Schwab1-8/+1
2020-07-30riscv: Cleanup unnecessary define in asm-offset.cGuo Ren1-5/+1
2020-07-30riscv: Enable context trackingGreentime Hu1-1/+15
2020-07-30riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORTGuo Ren1-1/+33
2020-06-09RISC-V: Remove do_IRQ() functionAnup Patel1-1/+3
2020-04-09Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-82/+61
2020-03-05riscv: fix seccomp reject syscall code pathTycho Andersen1-8/+3
2020-03-03RISC-V: Inline the assembly register save/restore macrosPalmer Dabbelt1-82/+61
2020-01-28Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-2/+2
2019-12-27riscv: reject invalid syscalls below -1David Abdurachmanov1-0/+1
2019-12-08sched/rt, riscv: Use CONFIG_PREEMPTIONThomas Gleixner1-2/+2
2019-11-22Merge branch 'next/nommu' into for-nextPaul Walmsley1-31/+54
2019-11-17riscv: add nommu supportChristoph Hellwig1-0/+11
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-31/+43
2019-10-29riscv: add support for SECCOMP and SECCOMP_FILTERDavid Abdurachmanov1-2/+25
2019-10-09RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider1-2/+1
2019-10-01RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt1-1/+20
2019-09-20riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen1-1/+5
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng1-3/+3
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel1-11/+11
2019-01-23RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=yVincent Chen1-1/+17
2019-01-07riscv: add audit supportDavid Abdurachmanov1-2/+2
2018-10-22RISC-V: SMP cleanup and new featuresPalmer Dabbelt1-1/+0
2018-10-22RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel1-1/+0
2018-10-22Extract FPU context operations from entry.SAlan Kao1-87/+0
2018-08-13RISC-V: implement low-level interrupt handlingChristoph Hellwig1-2/+2
2018-03-14RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handlerPalmer Dabbelt1-4/+3
2018-02-20RISC-V: Enable IRQ during exception handlingzongbox@gmail.com1-2/+3
2018-01-30riscv: disable SUM in the exception handlerChristoph Hellwig1-3/+6
2018-01-07riscv: rename SR_* constants to match the specChristoph Hellwig1-4/+4
2017-09-26RISC-V: Task implementationPalmer Dabbelt1-0/+464