Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-01-12 | riscv: cacheinfo: Fix using smp_processor_id() in preemptible | Kefeng Wang | 1 | -1/+10 |
2020-09-15 | riscv: Add cache information in AUX vector | Zong Li | 1 | -1/+31 |
2020-09-15 | riscv: Set more data to cacheinfo | Zong Li | 1 | -15/+51 |
2020-05-20 | riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structure | Yash Shah | 1 | -0/+17 |
2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 1 | -9/+1 |
2018-12-21 | RISC-V: Fix of_node_* refcount | Atish Patra | 1 | -0/+11 |
2018-10-22 | RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} | Palmer Dabbelt | 1 | -7/+0 |
2018-05-17 | drivers: base: cacheinfo: setup DT cache properties early | Jeremy Linton | 1 | -1/+0 |
2017-09-26 | RISC-V: Init and Halt Code | Palmer Dabbelt | 1 | -0/+105 |