summaryrefslogtreecommitdiffstats
path: root/arch/riscv/kernel/cacheinfo.c
AgeCommit message (Expand)AuthorFilesLines
2021-01-12riscv: cacheinfo: Fix using smp_processor_id() in preemptibleKefeng Wang1-1/+10
2020-09-15riscv: Add cache information in AUX vectorZong Li1-1/+31
2020-09-15riscv: Set more data to cacheinfoZong Li1-15/+51
2020-05-20riscv: cacheinfo: Implement cache_get_priv_group with a generic ops structureYash Shah1-0/+17
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2018-12-21RISC-V: Fix of_node_* refcountAtish Patra1-0/+11
2018-10-22RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}Palmer Dabbelt1-7/+0
2018-05-17drivers: base: cacheinfo: setup DT cache properties earlyJeremy Linton1-1/+0
2017-09-26RISC-V: Init and Halt CodePalmer Dabbelt1-0/+105